公开(公告)号：EP1470447A4

公开(公告)日：2007-10-10

申请号：EP02784585

申请日：2002-11-25

Applicant: IBM

Inventor： RANKIN JED H ,  SCHNEIDER CRAIN E ,  SMYTH JOHN S ,  WATTS ANDREW J

IPC: G03C5/00 ,  G01D18/00 ,  G03F7/20 ,  G06F17/50 ,  G06F19/00 ,  G21K5/00 ,  H01L21/027

CPC classification number: G03F7/70508 ,  G03F7/70558

Abstract: A method of implementing a new reticle for manufacturing semiconductor devices on a wafer which involves performing measurements (420) on the reticle and assigning an initial exposure dose (470) by using a predetermined algorithm (450). The exposure control system (490) utilizes reticle CD data (430, 440) for automatically calculating reticle exposure offset values, i.e. reticle factors (510). A correlation of reticle size deviations (500) to calculated reticle factors (510) is used to derive a reticle factor (510) for the new reticle. The derived reticle factor (510) is then used to predict (450) an initial exposure condition for the new reticle which is applied (470) to the lithography tool (410) for achieving a wafer design dimension.

公开(公告)号：EP2281303A4

公开(公告)日：2013-11-20

申请号：EP09798429

申请日：2009-06-18

Applicant: IBM

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/334 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.

公开(公告)号：EP1805795A4

公开(公告)日：2010-10-06

申请号：EP05809789

申请日：2005-10-11

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L27/12 ,  H01L21/336 ,  H01L21/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

公开(公告)号：EP1690294A4

公开(公告)日：2010-09-22

申请号：EP04810448

申请日：2004-11-05

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/66795

公开(公告)号：EP1581968A4

公开(公告)日：2007-04-18

申请号：EP02808339

申请日：2002-12-20

Applicant: IBM

Inventor： RANKIN JED H ,  ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J JR ,  FRIED DAVID M

IPC: H01L23/525 ,  H01L21/82 ,  H01L21/84 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).