公开(公告)号：EP1356498A4

公开(公告)日：2009-05-13

申请号：EP01990114

申请日：2001-12-13

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ENGEL BRETT H ,  HOINKIS MARK ,  MILLER JOHN A ,  SEO SOON-CHEON ,  WANG YUN-YU ,  WONG HON WONG

IPC: H01K3/10 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/50 ,  H01L23/52 ,  H01L23/532 ,  H05K3/02

CPC classification number: H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect (30, 50) and low-k interlayer dielectrics (40), a problem of open circuits after heat treatment was discovered and solved bz the use of a first liner layer of Cr (42), followed by a conformal liner layer of CVD TiN (46), followed in turn bz a final liner layer of Ta or TaN (48), thus improving adhesion between the via (50) and the underlying copper layer (30) while maintianing low resistance.

公开(公告)号：EP1397830A4

公开(公告)日：2009-03-11

申请号：EP01988335

申请日：2001-12-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/76858 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer (42) of Ti, followed by a conformal liner layer (46) of CVD TiN, followed in turn by a final liner layer (48) of TA or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the copper to an acceptable amount.

Abstract translation: 在具有铜互连和低k层间电介质的集成电路中，发现热处理后开路的问题，并通过使用Ti的第一衬垫层（42），随后使用CVD共形衬垫层（46） TiN，然后依次是TA或TaN的最终衬垫层（48），因此改善了通孔和下面的铜层之间的粘合性，同时将由Ti和铜之间的合金化引起的电阻的增加减少到可接受的量。

公开(公告)号：EP1356507A4

公开(公告)日：2008-05-21

申请号：EP01996224

申请日：2001-12-30

Applicant: IBM

Inventor： GIEWONT KENNETH J ,  BRODSKY STEPHEN BRUCE ,  CABRAL CYRIL JR ,  DOMENICUCCI ANTHONY G ,  RANSOM CRAIG MITCHELL ,  WANG YUN-YU ,  WILDMAN HORATIO S ,  WONG KWONG HON

IPC: C23C14/06 ,  C23C14/34 ,  H01L21/28 ,  H01L21/285 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/44

CPC classification number: C23C14/0094 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855

Abstract: A method is provided for forming a capping layer for a semiconductor structure including a silicide-forming metal (2) overlying silicon (1). According to the invention, a layer of nitride (51) is formed overlying the semiconductor structure and in contact with the silicide-forming metal (2). This layer is formed by sputtering form a target in an ambient characterized by a nitrogen flow less than about 45 sccm. The layer is therefore deficient in nitrogen, so that formation of an oxynitride at a native oxide layer (11) on the silicon is avoided and diffusion between the silicon (1) and the metal (2) is not inhibited.

公开(公告)号：EP2095409A4

公开(公告)日：2014-05-21

申请号：EP07842115

申请日：2007-09-10

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  WANG PING-CHUAN ,  WANG YUN-YU

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76847 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2033213A4

公开(公告)日：2012-08-01

申请号：EP07757974

申请日：2007-03-06

Applicant: IBM

Inventor： YANG DAEWON ,  LEE WOO-HYEONG ,  SU TAI-CHI ,  WANG YUN-YU

IPC: H01L21/31 ,  B05D3/00 ,  C23C16/34 ,  C23C16/505 ,  H01L21/318 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/505 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.