公开(公告)号：EP3076430B1

公开(公告)日：2017-08-30

申请号：EP16168570.6

申请日：2003-02-14

Applicant: Fujitsu Semiconductor Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji

IPC: H01L23/58 ,  G03F1/26 ,  H01L21/768 ,  G03F1/32

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

公开(公告)号：EP1837902B1

公开(公告)日：2017-05-24

申请号：EP07107063.5

申请日：2001-08-20

Applicant: Dow Global Technologies LLC

Inventor： Shaffer, Edward O. II ,  Howard, Kevin E. ,  Waeterloos, Joost J. M. ,  Hetzner, Jack E. ,  Townsend, Paul H. III ,  Mills, Lynne K. ,  Gombar-Fetner, Sheila ,  Wilson, Larry R.

IPC: H01L21/311 ,  H01L21/312 ,  C09D183/06 ,  H01L51/10

CPC classification number: H01L21/02118 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/3121 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention is a method comprising providing a substrate, forming a first layer on the substrate, wherein the first layer has a dielectric constant of less than 3.0 and comprises an organic polymer, applying an organosilicate resin over the first layer, removing a portion of the organosilicate resin to expose a portion of the first layer, and removing the exposed portions of the first layer. The invention is also an integrated circuit article comprising an active substrate containing transistors and an electrical interconnect structure containing a pattern of metal lines separated, at least partially, by layers or regions of an organic polymeric material having a dielectric constant of less than 3.0 and further comprising a layer of an organosilicate resin above at least one layer of the organic polymer material.

Abstract translation: 本发明是一种方法，该方法包括：提供衬底;在衬底上形成第一层，其中第一层具有小于3.0的介电常数并且包括有机聚合物;在第一层上施加有机硅酸酯树脂;除去部分 有机硅酸酯树脂以暴露第一层的一部分，并除去第一层的暴露部分。 本发明还是一种集成电路制品，其包括含有晶体管的有源衬底和含有金属线图案的电互连结构，所述金属线图案至少部分地由具有小于3.0的介电常数的有机聚合物材料的层或区域分开，并且进一步 包括在有机聚合物材料的至少一层之上的有机硅酸酯树脂层。

公开(公告)号：EP2264758B1

公开(公告)日：2017-03-01

申请号：EP10177318.2

申请日：2002-12-05

Applicant: Fujitsu Semiconductor Limited

Inventor： Watanabe, Kenichi ,  Shimizu, Noriyoshi ,  Suzuki, Takashi

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76811 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP3070740A1

公开(公告)日：2016-09-21

申请号：EP16168579.7

申请日：2003-02-14

Applicant: Fujitsu Semiconductor Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji ,  Mitani, Junichi

IPC: H01L23/58 ,  H01L21/768

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: There is provided a semiconductor device, comprising a substrate (101) that includes an integrated circuit region (1), first and second interlayer insulation films (108, 111, 112) formed above the substrate, and a reinforcing structure comprising a main-wall part (2) and a sub-wall part (3) which are formed in the first and second interlayer insulation films, wherein the main-wall part surrounds the integrated circuit region in a periphery thereof and the sub-wall part is provided apart from the main-wall part in a corner region of the semiconductor device and is located between the integrated circuit region and the first bend section of the main-wall part. Both the main-wall part and the sub-wall part are formed by metal-filled trenches (131, 132) in the first and second interlayer insulation films.

公开(公告)号：EP2706410B1

公开(公告)日：2016-08-03

申请号：EP13195857.1

申请日：2003-02-14

Applicant: Fujitsu Semiconductor Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji ,  Mitani, Junichi

IPC: G03F1/26 ,  H01L23/00 ,  H01L23/58 ,  H01L21/768

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

公开(公告)号：EP2388820A3

公开(公告)日：2015-07-01

申请号：EP11166511.3

申请日：2011-05-18

Applicant: Renesas Electronics Corporation

Inventor： Hijioka, Kenichiro ,  Kume, Ippei ,  Inoue, Naoya ,  Shirai, Hiroki ,  Kawahara, Jun ,  Hayashi, Yoshihiro

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/02 ,  H01L23/522

CPC classification number: H01L27/10894 ,  H01L21/76811 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has a substrate (1); a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit (200) formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element (19) embedded in the multi-layered interconnect; and a logic circuit (100) formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode (14), a capacitor insulating film (15), an upper electrode (16), an embedded electrode and an upper interconnect (18); the top surface of the upper interconnect, and the top surface of the interconnect (80) configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

公开(公告)号：EP2219882A4

公开(公告)日：2011-11-23

申请号：EP08850920

申请日：2008-09-29

Applicant: EKC TECHNOLOGY INC

Inventor： CUI HUA

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L21/02068 ,  H01L21/02063 ,  H01L21/76811 ,  H01L21/76813

公开(公告)号：EP1864322B1

公开(公告)日：2011-06-01

申请号：EP06727680.8

申请日：2006-03-20

Applicant: NXP B.V.

Inventor： BESLING, Willem F.A., Société Civile SPID

IPC: H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/76811 ,  H01L21/76814 ,  H01L21/76826 ,  H01L2221/1063

Abstract: A dual damascene process for forming conductive interconnects on an integrated circuit die. The process comprises providing a layer (16) of porous, ultra low-k (ULK) dielectric material in which a via opening (30) is subsequently formed. A thermally degradable polymeric ('porogen') material (42) is applied to the side walls of the opening (30) such that the porogen material penetrates deeply into the porous ULK dielectric material (thereby sealing the pores and increasing the density thereof). Once a conductive material (36) has been provided with the opening (30) and polished back by means of chemical mechanical polishing (CMP), the complete structure is subjected to a curing step to cause the porogen material (44) with the ULK dielectric layer (16) to decompose and evaporate, thereby restoring the porosity (and low-k value) of the dielectric layer (16).

公开(公告)号：EP1371090A4

公开(公告)日：2007-10-24

申请号：EP01990106

申请日：2001-12-10

Applicant: IBM

Inventor： GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763 ,  H01L23/48

CPC classification number: H01L21/76835 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/76811

Abstract: A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics. Moreover, the spun-on dielectrics of the hybrid low-k dielectric have distinctly different atomic compositions enabling control over the conductor resistance using the bottom spun-on dielectric (i.e., via dielectric) as an inherent etch stop layer for the upper spun-on dielectric (i.e., line dielectric).

公开(公告)号：EP1226604B1

公开(公告)日：2007-02-28

申请号：EP01945667.2

申请日：2001-06-28

Applicant: TOKYO ELECTRON LIMITED

Inventor： MAEKAWA, Kaoru ,  HOSHINO, Satohiko ,  SUGIURA, Masahito ,  ALLEGRETTI, Federica Tokyo Electron Europe Limited

IPC: H01L21/312 ,  H01L21/768 ,  H01L21/316 ,  H01L21/3105

CPC classification number: H01L21/76835 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02282 ,  H01L21/02299 ,  H01L21/02318 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829

Abstract: A method of fabricating a semiconductor device includes the steps of forming a first insulation film on a substrate by a spin-on process, applying a curing process to the first insulation film at a temperature of 380 - 500 C over a duration of 5 - 180 seconds, and forming a second insulation film on the first insulation film by a spin-on process.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：通过旋涂工艺在衬底上形成第一绝缘膜，在380-150℃的温度下对该第一绝缘膜施加固化工艺持续5-180秒 秒，并且通过旋涂工艺在第一绝缘膜上形成第二绝缘膜。