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    Sample-and-hold circuit for an interleaved analog-to-digital converter
    3.
    发明公开
    Sample-and-hold circuit for an interleaved analog-to-digital converter 审中-公开
    Abtast- und Halteschaltungfüreinen verschachtelten Analog-Digital-Wandler

    公开(公告)号：EP2977989A1

    公开(公告)日：2016-01-27

    申请号：EP14178665.7

    申请日：2014-07-25

    申请人： IMEC VZW

    发明人： Verbruggen, Bob ,  Deguchi, Kazuaki ,  Craninckx, Jan

    IPC分类号： G11C27/02

    CPC分类号： G11C27/02 ,  H03M1/1245

    摘要： The present invention relates to a sample-and-hold circuit (1) comprising
    - a transistor (11) arranged for switching between a sample mode and a hold mode,
    - a bootstrap circuit (2) arranged for maintaining in said sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in said hold mode, said bootstrap circuit comprising a bootstrap capacitance (21) arranged for being precharged to a given voltage during said hold mode, said bootstrap capacitance being connected between the source terminal and the gate terminal during said sample mode, characterised in that the bootstrap circuit comprises a switched capacitor charge pump (22) for generating that given voltage.

    摘要翻译： 本发明涉及一种采样和保持电路（1），包括：晶体管（11），布置成用于在采样模式和保持模式之间切换; - 自举电路（2），布置成用于在所述采样模式中保持电压 源极端子和晶体管的栅极端子之间的电平，独立于源极端子处的电压并被布置为在所述保持模式下关断晶体管，所述自举电路包括布置成预充电到给定电压的自举电容（21） 在所述保持模式期间，所述自举电容在所述采样模式期间连接在所述源极端子和所述栅极端子之间，其特征在于，所述自举电路包括用于产生所述给定电压的开关电容器电荷泵（22）。

    Method and circuit for bandwidth mismatch estimation in an a/d converter
    4.
    发明公开
    Method and circuit for bandwidth mismatch estimation in an a/d converter 有权
    的方法和电路用于在A / D转换器的带宽失配估计

    公开(公告)号：EP2953265A1

    公开(公告)日：2015-12-09

    申请号：EP14171580.5

    申请日：2014-06-06

    申请人： IMEC VZW

    发明人： Deguchi, Kazuaki ,  Verbruggen, Bob ,  Craninckx, Jan

    IPC分类号： H03M1/10 ,  H03M1/12

    CPC分类号： H03M1/0604 ,  H03M1/00 ,  H03M1/002 ,  H03M1/1071 ,  H03M1/109 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/14 ,  H03M1/468 ,  H03M2201/4233

    摘要： The invention relates to a method for estimating bandwidth mismatch in a time-interleaved A/D converter (10) comprising
    - precharging to a first state second terminals of capacitors (3) in each channel (1) of a plurality of channels and sampling (2) a reference analog input voltage signal (V ref ) applied via a first switchable path (6) whereby the sampled input voltage signal is received at first terminals of said capacitors,
    - setting in each channel said second terminals to a second state, thereby generating a further reference voltage signal (V diff ) at said first terminals,
    - applying said reference analog input voltage signal to said first terminals via a second switchable path (7), said second path having a given impedance being higher than the known impedance of said first path, thereby creating on said first terminals a non-zero settling error indicative of an incomplete transition from said further reference voltage signal to said reference analog input voltage signal,
    - quantizing said settling error, thereby obtaining an estimate of the non-zero settling error in each channel,
    - comparing said estimates of said non-zero settling errors of said channels and deriving therefrom an estimation of the bandwidth mismatch.