公开(公告)号：EP3188368A1

公开(公告)日：2017-07-05

申请号：EP16204137.0

申请日：2016-12-14

Applicant: Analog Devices, Inc.

Inventor： Zhao, Jialin ,  Meng, Qingdong ,  Dong, Yunzhi ,  Silva, Jose Barreiro

IPC: H03M1/10 ,  H03M1/38 ,  H03M3/00 ,  H03M1/16

CPC classification number: H03M1/1071 ,  H03M1/1038 ,  H03M1/16 ,  H03M1/38 ,  H03M1/46 ,  H03M3/412 ,  H03M3/464

Abstract: For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine timing mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology utilizes cross-correlation of each DAC unit elements (UEs) output to the entire modulator output to measure its timing mismatch error respectively. Specifically, the timing mismatch error is estimated using a ratio based on a peak value and a value for the next tap in the cross-correlation function. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

Abstract translation: 对于利用反馈数模转换器（DAC）进行转换的模数转换器（ADC），最终的模拟输出会受到反馈DAC误差的影响或失真。 可以实施数字测量技术来确定连续时间Δ-Σ调制器（CTDSM）中的反馈DAC或连续时间流水线调制器中的时序失配误差。 该方法利用输出到整个调制器输出的每个DAC单元元件（UE）的互相关来分别测量其时序失配误差。 具体而言，使用基于互相关函数中的下一个抽头的峰值和值的比率来估计定时不匹配误差。 获得的错误可以存储在查找表中，并在数字域或模拟域中完全纠正。

公开(公告)号：EP2525232A3

公开(公告)日：2014-12-24

申请号：EP12167933.6

申请日：2012-05-14

Applicant: PHOENIX CONTACT GmbH & Co. KG

Inventor： Rohs, Markus ,  Pott, Thomas

IPC: H03M1/10 ,  G01R35/00 ,  G01R19/25 ,  H03M1/12

CPC classification number: H03M1/1071 ,  G01R19/25 ,  G01R35/00 ,  H03M1/12

Abstract: Die Erfindung betrifft eine Messvorrichtung (1) mit wenigstens zwei Messkanälen (2a, 2b), jeder Messkanal (2a, 2b) umfassend einen A/D-Wandler (4a, 4b) für die Umwandlung einer analogen Spannung in einen digitalen Spannungswert, und eine Logikeinheit (5a, 5b), die mit dem A/D-Wandler (4a, 4b) verbunden ist, um den digitalen Spannungswert zu empfangen, wobei wenigstens ein Messkanal (2a, 2b) als sicherer Messkanal (2a, 2b) mit einem Multiplexer (3a, 3b) ausgeführt ist, wobei mit dem Multiplexer (3a, 3b) die analoge Spannung zwischen einer Messspannung (U Mess1 , U Mess2 ) und einer Referenzspannung (U Ref1 , U Ref2 ) umschaltbar ist, und die Logikeinheit (5a, 5b) wenigstens eines anderen Messkanals (2a, 2b) als Referenzerzeuger ausgeführt ist, um die Referenzspannung (U Ref1 , U Ref2 ) bereitzustellen und den Multiplexer (3a, 3b) zwischen der Messspannung (U Mess1 , U Mess2 ) und der Referenzspannung (U Ref1 , U Ref2 ) umzuschalten.

Abstract translation: 该装置具有测量通道（2a，2b），其具有用于将模拟电压值转换为数字电压值的模拟（A / D）转换器（4a，4b）。 逻辑单元（5a，5b）与A / D转换器连接，以便接收数字电压值。 基于数字电压值提供参考发生器来产生参考电压（Uref1，Uref2）。 多路复用器（3a，3b）在测量电压（UMess1，UMess2）和参考电压之间切换模拟电压。

公开(公告)号：EP2579052A1

公开(公告)日：2013-04-10

申请号：EP11786045.2

申请日：2011-05-18

Applicant: Zoomlion Heavy Industry Science and Technology Co., Ltd. ,  Hunan Zoomlion Special Vehicle Co. Ltd.

Inventor： ZHAN, Chunxin ,  LIU, Quan ,  LI, Xinyi ,  GUO, Jimei ,  FENG, Songsheng

IPC: G01R27/14 ,  H03M1/10

CPC classification number: H03M1/1071 ,  G01R27/14 ,  H03M1/12

Abstract: A method for measuring the resistance value of the conversion resistance of a current mode analog/digital converter, involves keeping a current signal inputted to the current mode analog/digital converter constant (S11); obtaining a first digital quantity AD 0 transformed by the current mode analog/digital converter (S12); connecting a resistance R j , of which precision is higher than that of the conversion resistance R z of the current mode analog/digital converter, with the conversion resistance R z in parallel (S13); obtaining again a second digital quantity AD 1 transformed by the current mode analog/digital converter (S14); acquiring the resistance value of the conversion resistance R z by the following formula(I):

wherein, R 1 is the acquired resistance value of the conversion resistance R z , and R 2 is the resistance value of the resistance R j , of which precision is higher than that of the conversion resistance R z . The method can improve the precision of measuring and controlling the measured physical objects.

Abstract translation: 测量电流型模数转换器的转换电阻的电阻值的方法涉及将输入到电流型模数转换器的电流信号保持恒定（S11）; 获得由当前模式模数转换器转换的第一数字量AD0（S12）; 将精度高于电流型模数转换器的转换电阻Rz的电阻Rj与转换电阻Rz并联（S13）; 再次获得由当前模式模数转换器转换的第二数字量AD1（S14）; 通过以下公式（I）获取转换电阻Rz的电阻值：其中，R1是获取的转换电阻Rz的电阻值，R2是电阻Rj的电阻值，其精度高于 转换电阻Rz。 该方法可以提高测量和控制被测物体的精度。

公开(公告)号：EP1795870A3

公开(公告)日：2013-02-27

申请号：EP06024569.3

申请日：2006-11-28

Applicant: Dr. Johannes Heidenhain GmbH

Inventor： Yamamoto, Takeshi

IPC: G01D5/245 ,  G05B19/19 ,  G06F11/07 ,  H03M1/10 ,  H03M1/14 ,  G01D5/244

CPC classification number: G01D5/24466 ,  G01D5/2451 ,  G05B2219/37154 ,  H03M1/1071 ,  H03M1/143 ,  H03M1/30

Abstract: Die Erfindung betrifft eine Schaltungsanordnung, sowie ein Verfahren zur Feststellung von Zählfehlern in einer Positionsmesseinrichtung, die eine dem Positionsverschiebungsausmaß eines zu messenden Objekts entsprechende Impulsreihe feststellt, wobei mittels eines Zählers (4) Zählsignale, die aus wenigstens einem verdoppelten, verdreifachten oder vervierfachten Basissignal (Phase A, Phase B) zur Berechnung des Positionsverschiebungsausmaßes erzeugt werden, gezählt werden und mittels eines Vergleichers (6) wenigstens ein Ausgangssignal (Z0, Z1) des Zählers (4) mit einem aus dem wenigstens einen Basissignal (Phase A, Phase B) abgeleiteten Vergleichssignal verglichen wird. Bei Bestehen einer bestimmten Beziehung gibt der Vergleicher (6) ein Zählfehlerausgangssignal (E) aus.

公开(公告)号：EP2372916A2

公开(公告)日：2011-10-05

申请号：EP11250312.3

申请日：2011-03-16

Applicant: Ateeda Ltd.

Inventor： Hamilton, David , Ateeda Ltd. ,  Sharp, Gordon , Ateeda Ltd.

IPC: H03M1/12

CPC classification number: H03M1/1071 ,  G06F17/18 ,  H03M1/109 ,  H03M1/12

Abstract: A histogram-based method for testing an electronic converter device, such as an analogue to digital converter, the method comprising: defining at least one histogram hyperbin arranged to store hits for at least one subrange of output codes; applying an input test stimulus to an input of the device to test a subrange of output codes matched to the hyperbin; and accumulating the histogram.

Abstract translation: 一种用于测试诸如模数转换器的电子转换器装置的基于直方图的方法，所述方法包括：定义至少一个布置成存储输出码的至少一个子范围的命中的直方图超列; 将输入测试激励应用到所述设备的输入端以测试与所述超字节匹配的输出代码的子范围; 并累积直方图。

公开(公告)号：EP1829218A2

公开(公告)日：2007-09-05

申请号：EP05854789.4

申请日：2005-12-16

Applicant: Teradyne, Inc.

Inventor： WALKER, Ernest P. ,  SARTSCHEV, Ronald A.

IPC: H03M1/10 ,  H03M1/06

CPC classification number: H03M1/1071

Abstract: In one aspect, the invention is an integrated circuit (IC) for use in testing an analog-to-digital (ADC) converter includes a first channel of a parametric measurement unit (PMU) configured to send a force signal to the ADC. The IC also includes a first digital-to-analog converter (DAC) connected to the first channel of the PMU. The DAC has a DC level of accuracy of less than 1 millivolt.In another aspect, the invention is an integrated circuit (IC) for use in testing a digital-to-analog-converter-device-under-test (DACDUT). The IC includes a first channel of a parametric measurement unit (PMU) configured to send a force signal to the DACDUT and including an output port for taking measurements, a first digital-to-analog converter (DAC) connected to the first channel of the PMU and a PMU measurement path connected to the output port having a DC level of accuracy of less than 1 mV.

公开(公告)号：EP1339169B1

公开(公告)日：2006-08-30

申请号：EP02023227.8

申请日：2002-10-16

Applicant: Agilent Technologies, Inc.

Inventor： Poulton, Kenneth D. ,  Neff, Robert M. R. ,  Holcomb, Matthew S. ,  Kang, James

IPC: H03M1/10

CPC classification number: H03M1/1071 ,  H03M1/0692 ,  H03M1/1061 ,  H03M1/447

公开(公告)号：EP0282154A3

公开(公告)日：1990-09-12

申请号：EP88300715.5

申请日：1988-01-28

Applicant: TEKTRONIX INC.

Inventor： Traa, Einar Oddbjorn

IPC: H03M1/36

CPC classification number: H03M1/1071 ,  H03M1/361

Abstract: An analog-to-digital converter (10) comprises a set of comparators (12a-12f) for providing a set of different output signals whose logic states are a function of an analog input signal voltage and one or more reference voltage signals supplied by a resistive network (16). The comparators are connected to a decoder (20) for processing the thermometer code outputs of the comparators to generate a digital word output corresponding to the voltage amplitude of the analog signal. Several of the comparators are also connected to an error checking network (22), including a preconditioning circuit (100) and a detection circuit (102) for processing these comparator outputs to provide an error signal whenever one or more of the comparators are not operating properly. The error checking network and decoder are connected to an error correction circuit (26) for correcting the digital word signal in accordance with the error signal. Also, comparator circuits are provided which are well-adapted for high-­speed operation and error checking.

公开(公告)号：EP0100391B1

公开(公告)日：1990-04-04

申请号：EP83100151.6

申请日：1983-01-11

Applicant: ROBERT BOSCH GMBH

Inventor： Saul, Gert, Ing. grad. ,  Meister, Werner, Ing. grad.

IPC: G01D5/243 ,  G05B19/33 ,  G05B19/35

CPC classification number: G05B19/4062 ,  G01D5/243 ,  G05B19/33 ,  G05B2219/37541 ,  H03M1/1071 ,  H03M1/485

公开(公告)号：EP0282147A2

公开(公告)日：1988-09-14

申请号：EP88300271.9

申请日：1988-01-13

Applicant: TEKTRONIX INC.

Inventor： Traa, Einar O.

IPC: H03M1/36

CPC classification number: H03M1/1071 ,  H03M1/361

Abstract: An error correction circuit (16) corrects errors in the thermometer code (T₁-T₇) developed by a parallel or "flash" analog-to-digital converter (10). The error correction circuit employs plural similar bit exchange modules (34) of which each includes a 2-input OR gate (46) having common inputs (48 and 50) that constitute the inputs of the bit exchange module. The output (52) of the AND gate and the output (54) of the OR gate constitute the outputs of the bit exchange module. The bit exchange modules receive the digital-to-analog converter thermometer code and are interconnected to correct errors therein resulting from the presence of more than one transition between different logic states for adjacent bits in the thermometer code. The error correction circuit manipulates the thermometer code bits to provide a corrected thermometer code (T 1C -T 7C ) that has only one transition between different logic states for adjacent bits thereof.

Abstract translation: 纠错电路（16）校正由并行或“闪存”模数转换器（10）开发的温度计代码（T1-T7）中的错误。 误差校正电路采用多个类似的比特交换模块（34），其中每个包括构成比特交换模块的输入的公共输入（48和50）的2-输入或门（46）。 与门的输出（52）和或门的输出（54）构成比特交换模块的输出。 位交换模块接收数模转换器温度计代码，并且互连以校正其中的错误，这是由于温度计代码中的相邻位的不同逻辑状态之间存在多于一个的转换。 误差校正电路操作温度计代码位以提供在其相邻位之间仅在不同逻辑状态之间仅有一个转换的校正温度计代码（T1C-T7C）。