公开(公告)号：EP1236088B9

公开(公告)日：2008-10-08

申请号：EP00959711.3

申请日：2000-08-31

申请人： Intel Corporation

发明人： WOLRICH, Gilbert ,  ADILETTA, Matthew, J. ,  WHEELER, William ,  BERNSTEIN, Debra ,  HOOPER, Donald

IPC分类号： G06F9/00 ,  G06F12/00

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/30058 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851

摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD_3 ... THREAD_0). The processor maintains execution threads (THREAD_3 ... THREAD_0). The execution threads (THREAD_3 ... THREAD_0) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD_3 ... THREAD_0).

摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文（THREAD_3 ... THREAD_0）的多个微引擎。 处理器维护执行线程（THREAD_3 ... THREAD_0）。 执行线程（THREAD_3 ... THREAD_0）访问组织成多个相对可寻址的，每个线程相对可寻址的寄存器窗口（THREAD_3 ... THREAD_0）的寄存器组。

公开(公告)号：EP1282862A2

公开(公告)日：2003-02-12

申请号：EP00993654.3

申请日：2000-12-06

申请人： INTEL CORPORATION

发明人： WOLRICH, Gilbert ,  BERNSTEIN, Debra ,  ADILETTA, Matthew, J. ,  WHEELER, William

IPC分类号： G06F13/00

CPC分类号： G06F13/1642

摘要： A controller for a random access memory has control logic, including an arbiter that detects a status of outstanding memory references. The controller selects a memory reference from one of a plurality queues of memory references. The control logic is responsive to a memory reference chaining bit that when set allows for special handling of contiguous memory references.

公开(公告)号：EP1244959A2

公开(公告)日：2002-10-02

申请号：EP00984105.7

申请日：2000-12-08

申请人： INTEL CORPORATION

发明人： WOLRICH, Gilbert ,  CUTTER, Daniel ,  WHEELER, William ,  ADILETTA, Matthew, J. ,  BERNSTEIN, Debra

IPC分类号： G06F9/00

CPC分类号： G06F9/52

摘要： Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if the read lock memory reference request is requesting access to an unlocked memory location and the read lock miss queue contains at least one read lock memory reference request.

公开(公告)号：EP1236094A1

公开(公告)日：2002-09-04

申请号：EP00961457.9

申请日：2000-08-31

申请人： INTEL CORPORATION

发明人： WOLRICH, Gilbert ,  ADILETTA, Matthew, J. ,  WHEELER, William ,  BERNSTEIN, Debra ,  HOOPER, Donald

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/30058 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851

摘要： A parallel hardware-based multithreaded processor (12) is described. The processor (12) includes a general purpose processor that coordinates system functions and a plurality of microengines (22a-22f) that support multiple hardware threads or contexts. The processor (12) also includes a memory control system (16) that has a first memory controller (26a) that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller (26b) that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed.

公开(公告)号：EP1245097B1

公开(公告)日：2013-07-03

申请号：EP00984108.1

申请日：2000-12-07

申请人： Intel Corporation

发明人： WOLRICH, Gilbert ,  BERNSTEIN, Debra ,  ADILETTA, Matthew, J. ,  HOOPER, Donald, F.

IPC分类号： H04L12/953

CPC分类号： H04L49/351 ,  H04L49/102 ,  H04L49/352

公开(公告)号：EP1236097A1

公开(公告)日：2002-09-04

申请号：EP00959712.1

申请日：2000-08-31

申请人： INTEL CORPORATION

发明人： WOLRICH, Gilbert ,  ADILETTA, Matthew, J. ,  WHEELER, William ,  BERNSTEIN, Debra ,  HOOPER, Donald

IPC分类号： G06F9/44

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/30058 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851

摘要： A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor (12) can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified bit of a register (80, 78, 76b) being set or cleared and which specifies which bit of the specified register to use as a branch control bit.

公开(公告)号：EP1236092A1

公开(公告)日：2002-09-04

申请号：EP00959717.0

申请日：2000-08-31

申请人： INTEL CORPORATION

发明人： WOLRICH, Gilbert ,  ADILETTA, Matthew, J. ,  WHEELER, William ,  BERNSTEIN, Debra ,  HOOPER, Donald

IPC分类号： G06F9/30

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/30058 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851

摘要： A processor such as a multithreaded hardware based processor (12) is described. The processor (12) includes a computer instruction (20) that is a branch instruction that causes a branch in execution of an instruction stream based on any specified value being true or false. The instruction also includes a token that specifies the number of instruction of instructions following the branch instruction to execute before performing the branch operation.

公开(公告)号：EP1214660A1

公开(公告)日：2002-06-19

申请号：EP00954126.9

申请日：2000-08-17

申请人： Intel Corporation

发明人： ADILETTA, Matthew, J. ,  WHEELER, William ,  REDFIELD, James ,  CUTTER, Daniel ,  WOLRICH, Gilbert

IPC分类号： G06F13/16 ,  G06F9/46

CPC分类号： G06F13/1642

摘要： A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

公开(公告)号：EP1212869A1

公开(公告)日：2002-06-12

申请号：EP00955560.8

申请日：2000-08-14

申请人： Intel Corporation

发明人： WOLRICH, Gilbert ,  ADILETTA, Matthew, J. ,  CYR, John

IPC分类号： H04L12/56

CPC分类号： H04L49/10 ,  H04L49/101 ,  H04L49/254 ,  H04L49/3045 ,  H04L49/45

摘要： A switch fabric includes a first plurality of data switches each having a plurality of input ports and a plurality of output ports the plurality of switches capable of switching any of its input ports to any of its output ports with the plurality of data switches having inputs coupled to a plurality of input buses so that a first byte of a first one of the input buses is coupled to a first one of the plurality of switches, and a succeeding byte of the first input bus is coupled to a succeeding one of the plurality of switches.

公开(公告)号：EP3488573A1

公开(公告)日：2019-05-29

申请号：EP17831516.4

申请日：2017-06-22

申请人： INTEL Corporation

发明人： GORIUS, Aaron ,  WILDE, Myles ,  ADILETTA, Matthew, J.

IPC分类号： H04L12/931 ,  H04L12/933 ,  H04L12/861 ,  H04Q11/00