公开(公告)号：EP1493081B1

公开(公告)日：2010-11-03

申请号：EP03734963.6

申请日：2003-01-16

申请人： Intel Corporation

发明人： ADILETTA, Matthew ,  BERNSTEIN, Debra ,  ROSENBLUTH, Mark ,  WOLRICH, Gilbert

IPC分类号： G06F9/38 ,  G06F13/16

CPC分类号： G06F9/3824 ,  G06F9/3851

摘要： A method for transferring data between programming agents and memory resources. The method includes transferring data between a processing agent and a memory resource, designating the memory resource for pushing the data to the processing agent via a push bus having a plurality of sources that arbitrate use of the push bus, and designating the memory resource for receiving the data from the processing agent via a pull bus having a plurality of destinations that arbitrate use of the pull bus.

公开(公告)号：EP1282862B1

公开(公告)日：2010-04-14

申请号：EP00993654.3

申请日：2000-12-06

申请人： Intel Corporation

发明人： WOLRICH, Gilbert ,  BERNSTEIN, Debra ,  ADILETTA, Matthew, J. ,  WHEELER, William

IPC分类号： G06F13/00

CPC分类号： G06F13/1642

公开(公告)号：EP1242883B1

公开(公告)日：2006-09-13

申请号：EP00992412.7

申请日：2000-12-08

申请人： INTEL CORPORATION

发明人： WOLRICH, Gilbert ,  HOOPER, Donald ,  BERNSTEIN, Debra ,  ADILETTA, Matthew, J. ,  WHEELER, William

IPC分类号： G06F9/54 ,  G06F9/50

CPC分类号： G06F9/4843 ,  G06F9/3851

摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.

公开(公告)号：EP1236088A1

公开(公告)日：2002-09-04

申请号：EP00959711.3

申请日：2000-08-31

申请人： INTEL CORPORATION

发明人： WOLRICH, Gilbert ,  ADILETTA, Matthew, J. ,  WHEELER, William ,  BERNSTEIN, Debra ,  HOOPER, Donald

IPC分类号： G06F9/00 ,  G06F12/00

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/30058 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851

摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD_3 ... THREAD_0). The processor maintains execution threads (THREAD_3 ... THREAD_0). The execution threads (THREAD_3 ... THREAD_0) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD_3 ... THREAD_0).

公开(公告)号：EP1221086A1

公开(公告)日：2002-07-10

申请号：EP00959265.0

申请日：2000-08-17

申请人： Intel Corporation

发明人： BERNSTEIN, Debra ,  HOOPER, Donald, F. ,  ADILETTA, Matthew, J. ,  WOLRICH, Gilbert ,  WHEELER, William

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3012 ,  G06F9/30076 ,  G06F9/30127 ,  G06F9/3851

摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

公开(公告)号：EP1245097B1

公开(公告)日：2013-07-03

申请号：EP00984108.1

申请日：2000-12-07

申请人： Intel Corporation

发明人： WOLRICH, Gilbert ,  BERNSTEIN, Debra ,  ADILETTA, Matthew, J. ,  HOOPER, Donald, F.

IPC分类号： H04L12/953

CPC分类号： H04L49/351 ,  H04L49/102 ,  H04L49/352

公开(公告)号：EP1604493A2

公开(公告)日：2005-12-14

申请号：EP03774453.9

申请日：2003-08-04

申请人： INTEL CORPORATION

发明人： WOLRICH, Gilbert ,  SWEENEY, John ,  GUILFORD, James ,  ROSENBLUTH, Mark ,  BERNSTEIN, Debra

IPC分类号： H04L12/56 ,  G06F1/00

CPC分类号： H04L49/9047 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031

摘要： A method of managing a free list and ring data structure, which may be used to store journaling information, by storing and modifying information describing a structure of the free list or ring data structure in a cache memory that may also be used to store information describing a structure of a queue of buffers.

公开(公告)号：EP1421504A1

公开(公告)日：2004-05-26

申请号：EP02778201.0

申请日：2002-08-27

申请人： INTEL CORPORATION

发明人： ROSENBLUTH, Mark ,  WOLRICH, Gilbert ,  BERNSTEIN, Debra ,  WILDE, Myles ,  ADILETTA, Matthew

IPC分类号： G06F13/40 ,  G06F13/42

CPC分类号： G06F13/364 ,  G06F13/4004

摘要： A bus mechanism to control information exchanges between bus masters and bus targets over a bus structure that includes separate command, push and pull data buses. Commands are generated by bus masters and are interpreted by bus targets on a per-target basis. Each bus target controls the servicing of a command intended for such target by controlling the transfer of push data over the push bus to a bus master specified in the command as a destination, for a push operation type, and by controlling the transfer of pull data over the pull bus to the target from a bus master specified in the command as a destination, for a pull operation type. Arbitration logic associated with each bus is used to control the flow of the information exchanges on that bus.

公开(公告)号：EP1236097A1

公开(公告)日：2002-09-04

申请号：EP00959712.1

申请日：2000-08-31

申请人： INTEL CORPORATION

发明人： WOLRICH, Gilbert ,  ADILETTA, Matthew, J. ,  WHEELER, William ,  BERNSTEIN, Debra ,  HOOPER, Donald

IPC分类号： G06F9/44

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/30058 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851

摘要： A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor (12) can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified bit of a register (80, 78, 76b) being set or cleared and which specifies which bit of the specified register to use as a branch control bit.

公开(公告)号：EP1236092A1

公开(公告)日：2002-09-04

申请号：EP00959717.0

申请日：2000-08-31

申请人： INTEL CORPORATION

发明人： WOLRICH, Gilbert ,  ADILETTA, Matthew, J. ,  WHEELER, William ,  BERNSTEIN, Debra ,  HOOPER, Donald

IPC分类号： G06F9/30

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/30058 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851

摘要： A processor such as a multithreaded hardware based processor (12) is described. The processor (12) includes a computer instruction (20) that is a branch instruction that causes a branch in execution of an instruction stream based on any specified value being true or false. The instruction also includes a token that specifies the number of instruction of instructions following the branch instruction to execute before performing the branch operation.