公开(公告)号：EP3805921A2

公开(公告)日：2021-04-14

申请号：EP20199439.9

申请日：2011-09-30

Applicant: INTEL Corporation

Inventor： VALENTINE, Robert C. ,  SAN ADRIAN, Jesus Corbal ,  SANS, Roger Espasa ,  CAVIN, Robert D. ,  TOLL, Bret L. ,  DURAN, Santiago Galan ,  WIEDEMEIER, Jeffrey G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind Baburao ,  GROCHOWSKI, Edward Thomas ,  HALL, Jonathan Cannon ,  BRADFORD, Dennis R. ,  OULD-AHMED-VALL, Elmoustapha ,  ABEL, James C. ,  CHARNEY, Mark ,  ABRAHAM, Seth ,  SAIR, Suleyman ,  FORSYTH, Andrew Thomas ,  YOUNT, Charles ,  WU, Lisa

IPC: G06F9/30

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：EP3812900A1

公开(公告)日：2021-04-28

申请号：EP20207505.7

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： SANKARAN, Rajesh M. ,  NEIGER, Gilbert ,  RANGANATHAN, Narayan ,  VAN DOREN, Stephen R. ,  NUZMAN, Joseph ,  MCDONNELL, Niall D. ,  O'HANLON, Michael A. ,  MOSUR, Lokpraveen B. ,  DRYSDALE, Tracy Garrett ,  NURVITADHI, Eriko ,  MISHRA, Asit K. ,  VENKATESH, Ganesh ,  MARR, Deborah T. ,  CARTER, Nicholas P. ,  PEARCE, Jonathan D. ,  GROCHOWSKI, Edward T. ,  GRECO, Richard J. ,  VALENTINE, Robert ,  CORBAL, Jesus ,  FLETCHER, Thomas D. ,  BRADFORD, Dennis R. ,  MANLEY, Dwight P. ,  CHARNEY, Mark J. ,  COOK, Jeffrey J. ,  CAPRIOLI, Paul ,  YAMADA, Koichi ,  GLOSSOP, Kent D. ,  SHEFFIELD, David B.

IPC: G06F9/48 ,  G06F9/38

Abstract: The present disclosure provides apparatus comprising a silicon interposer, a communication fabric, an accelerator die comprising a plurality of computing elements to simultaneously perform operations on a plurality of matrix data elements. The apparatus comprising a plurality of dot-product engines, the plurality of dot-product engines to compute a plurality of dot products on the matrix data elements to generate a plurality of result matrix data elements, a buffer or cache to store a plurality of matrix data elements a memory controller coupled to the communication fabric and a stacked DRAM that stacks a plurality of DRAM dies vertically on the silicon interposer substrate coupled to the accelerator die.

公开(公告)号：EP3563235A1

公开(公告)日：2019-11-06

申请号：EP16925260.8

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： SANKARAN, Rajesh M. ,  NEIGER, Gilbert ,  RANGANATHAN, Narayan ,  VAN DOREN, Stephen R. ,  NUZMAN, Joseph ,  MCDONNELL, Niall D. ,  O'HANLON, Michael A. ,  MOSUR, Lokpraveen B. ,  DRYSDALE, Tracy Garrett ,  NURVITADHI, Eriko ,  MISHRA, Asit K. ,  VENKATESH, Ganesh ,  MARR, Deborah T. ,  CARTER, Nicholas P. ,  PEARCE, Jonathan D. ,  GROCHOWSKI, Edward T. ,  GRECO, Richard J. ,  VALENTINE, Robert ,  CORBAL, Jesus ,  FLETCHER, Thomas D. ,  BRADFORD, Dennis R. ,  MANLEY, Dwight P. ,  CHARNEY, Mark J. ,  COOK, Jeffrey J. ,  CAPRIOLI, Paul ,  YAMADA, Koichi ,  GLOSSOP, Kent D. ,  SHEFFIELD, David B.

IPC: G06F9/48 ,  G06F9/38

公开(公告)号：EP2798504A1

公开(公告)日：2014-11-05

申请号：EP11878342.2

申请日：2011-12-29

Applicant: Intel Corporation

Inventor： FORSYTH, Andrew Thomas ,  BRADFORD, Dennis R.

IPC: G06F13/14 ,  G06F9/30 ,  G06F9/305

CPC classification number: G06F9/30036 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30145 ,  G06F9/3818 ,  G06F9/3838

Abstract: An apparatus includes a decode unit to decode a permute instruction and a vector conflict instruction. A vector execution unit is coupled with the decode unit and includes a fully-connected interconnect. The fully-connected interconnect has at least four inputs to receive at least four corresponding data elements of at least one source vector. The fully-connected interconnect has at least four outputs. Each of the at least four inputs is coupled with each of the at least four outputs. The execution unit also includes a permute instruction execution logic coupled with the at least four outputs and operable to store a first vector result in response to the permute instruction. The execution unit also includes a vector conflict instruction execution logic coupled with the at least four outputs and operable to store a second vector result in a destination storage location in response to the vector conflict instruction.

公开(公告)号：EP4089531A1

公开(公告)日：2022-11-16

申请号：EP22180798.5

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： SANKARAN, Rajesh M. ,  NEIGER, Gilbert ,  RANGANATHAN, Narayan ,  VAN DOREN, Stephen R. ,  NUZMAN, Joseph ,  MCDONNELL, Niall D. ,  O'HANLON, Michael A. ,  MOSUR, Lokpraveen B. ,  DRYSDALE, Tracy Garrett ,  NURVITADHI, Eriko ,  MISHRA, Asit K. ,  VENKATESH, Ganesh ,  MARR, Deborah T. ,  CARTER, Nicholas P. ,  PEARCE, Jonathan D. ,  GROCHOWSKI, Edward T. ,  GRECO, Richard J. ,  VALENTINE, Robert ,  CORBAL, Jesus ,  FLETCHER, Thomas D. ,  BRADFORD, Dennis R. ,  MANLEY, Dwight P. ,  CHARNEY, Mark J. ,  COOK, Jeffrey J. ,  CAPRIOLI, Paul ,  YAMADA, Koichi ,  GLOSSOP, Kent D. ,  SHEFFIELD, David B.

IPC: G06F9/38 ,  G06F12/08

Abstract: The present disclosure provides an apparatus comprising an accelerator; a local memory comprising a plurality of stacked dynamic random access memory, DRAM, dies; a silicon bridge to couple the accelerator to the plurality of stacked DRAM dies, wherein connections between the accelerator and the plurality of stacked DRAM dies run through the silicon bridge. The accelerator comprising a plurality of processing elements to perform processing tasks allocated by an external processor; a cache coherent interface to couple the accelerator to the external processor, the cache coherent interface to ensure that data stored in the local memory and/or an accelerator cache is coherent with data stored in a system memory and caches of the external processor; and logic to map a virtual memory space to heterogeneous forms of physical system memory including the local memory and the system memory, the accelerator and the external processor to both use the virtual memory space to access corresponding portions of the local memory and the system memory.

公开(公告)号：EP4398113A3

公开(公告)日：2024-11-06

申请号：EP24178028.7

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： SANKARAN, Rajesh M. ,  NEIGER, Gilbert ,  RANGANATHAN, Narayan ,  VAN DOREN, Stephen R. ,  NUZMAN, Joseph ,  MCDONNELL, Niall D. ,  O'HANLON, Michael A. ,  MOSUR, Lokpraveen B. ,  DRYSDALE, Tracy Garrett ,  NURVITADHI, Eriko ,  MISHRA, Asit K. ,  VENKATESH, Ganesh ,  MARR, Deborah T. ,  CARTER, Nicholas P. ,  PEARCE, Jonathan D. ,  GROCHOWSKI, Edward T. ,  GRECO, Richard J. ,  VALENTINE, Robert ,  CORBAL, Jesus ,  FLETCHER, Thomas D. ,  BRADFORD, Dennis R. ,  MANLEY, Dwight P. ,  CHARNEY, Mark J. ,  COOK, Jeffrey J. ,  CAPRIOLI, Paul ,  YAMADA, Koichi ,  GLOSSOP, Kent D. ,  SHEFFIELD, David B.

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38

Abstract: The present disclosure provides a processor including a processor core. The processor core includes: a decoder to decode at least one instruction native to the processor core; one or more execution units to execute at least one decoded instruction, the at least one decoded instruction corresponding to an acceleration begin instruction, the acceleration begin instruction to indicate a start of a region of code to be offloaded to an accelerator.

公开(公告)号：EP4398113A2

公开(公告)日：2024-07-10

申请号：EP24178028.7

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： SANKARAN, Rajesh M. ,  NEIGER, Gilbert ,  RANGANATHAN, Narayan ,  VAN DOREN, Stephen R. ,  NUZMAN, Joseph ,  MCDONNELL, Niall D. ,  O'HANLON, Michael A. ,  MOSUR, Lokpraveen B. ,  DRYSDALE, Tracy Garrett ,  NURVITADHI, Eriko ,  MISHRA, Asit K. ,  VENKATESH, Ganesh ,  MARR, Deborah T. ,  CARTER, Nicholas P. ,  PEARCE, Jonathan D. ,  GROCHOWSKI, Edward T. ,  GRECO, Richard J. ,  VALENTINE, Robert ,  CORBAL, Jesus ,  FLETCHER, Thomas D. ,  BRADFORD, Dennis R. ,  MANLEY, Dwight P. ,  CHARNEY, Mark J. ,  COOK, Jeffrey J. ,  CAPRIOLI, Paul ,  YAMADA, Koichi ,  GLOSSOP, Kent D. ,  SHEFFIELD, David B.

IPC: G06F12/08

CPC classification number: G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30189 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/4411 ,  G06F9/45504 ,  G06F9/4881 ,  G06F9/5027 ,  G06F9/30181 ,  G06F9/30076 ,  Y02D10/00 ,  G06F9/38585 ,  G06F9/3858

Abstract: The present disclosure provides a processor including a processor core. The processor core includes: a decoder to decode at least one instruction native to the processor core; one or more execution units to execute at least one decoded instruction, the at least one decoded instruction corresponding to an acceleration begin instruction, the acceleration begin instruction to indicate a start of a region of code to be offloaded to an accelerator.

公开(公告)号：EP3422178A3

公开(公告)日：2019-04-10

申请号：EP18177235.1

申请日：2011-09-30

Applicant: Intel Corporation

Inventor： VALENTINE, Robert C. ,  SAN ADRIAN, Jesus Corbal ,  SANS, Roger Espasa ,  CAVIN, Robert D. ,  TOLL, Bret L. ,  DURAN, Santiago Galan ,  WIEDEMEIER, Jeffrey G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind Baburao ,  GROCHOWSKI, Edward Thomas ,  HALL, Jonathan Cannon ,  BRADFORD, Dennis R. ,  OULD-AHMED-VALL, Elmoustapha ,  ABEL, James C. ,  CHARNEY, Mark ,  ABRAHAM, Seth ,  SAIR, Suleyman ,  FORSYTH, Andrew Thomas ,  YOUNT, Charles ,  WU, Lisa

IPC: G06F9/30

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：EP3422178A2

公开(公告)日：2019-01-02

申请号：EP18177235.1

申请日：2011-09-30

Applicant: Intel Corporation

Inventor： VALENTINE, Robert C. ,  SAN ADRIAN, Jesus Corbal ,  SANS, Roger Espasa ,  CAVIN, Robert D. ,  TOLL, Bret L. ,  DURAN, Santiago Galan ,  WIEDEMEIER, Jeffrey G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind Baburao ,  GROCHOWSKI, Edward Thomas ,  HALL, Jonathan Cannon ,  BRADFORD, Dennis R. ,  OULD-AHMED-VALL, Elmoustapha ,  ABEL, James C. ,  CHARNEY, Mark ,  ABRAHAM, Seth ,  SAIR, Suleyman ,  FORSYTH, Andrew Thomas ,  YOUNT, Charles ,  WU, Lisa

IPC: G06F9/30

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：EP4120070A1

公开(公告)日：2023-01-18

申请号：EP22193012.6

申请日：2016-12-31

Applicant: INTEL Corporation

Inventor： SANKARAN, Rajesh M. ,  NEIGER, Gilbert ,  RANGANATHAN, Narayan ,  VAN DOREN, Stephen R. ,  NUZMAN, Joseph ,  MCDONNELL, Niall D. ,  O'HANLON, Michael A. ,  MOSUR, Lokpraveen B. ,  DRYSDALE, Tracy Garrett ,  NURVITADHI, Eriko ,  MISHRA, Asit K. ,  VENKATESH, Ganesh ,  MARR, Deborah T. ,  CARTER, Nicholas P. ,  PEARCE, Jonathan D. ,  GROCHOWSKI, Edward T. ,  GRECO, Richard J. ,  VALENTINE, Robert ,  CORBAL, Jesus ,  FLETCHER, Thomas D. ,  BRADFORD, Dennis R. ,  MANLEY, Dwight P. ,  CHARNEY, Mark J. ,  COOK, Jeffrey J. ,  CAPRIOLI, Paul ,  YAMADA, Koichi ,  GLOSSOP, Kent D. ,  SHEFFIELD, David B.

IPC: G06F9/30

Abstract: The present disclosure provides a method and an apparatus comprising a decoder to decode an enqueue command instruction, execution circuitry, where execution of the enqueue command instruction causes the execution circuitry to: generate a work descriptor based, at least in part, on data from a source operand of the enqueue command instruction, the work descriptor comprising a plurality of fields including an operation field to specify one or more operations to be performed, a flag to indicate whether the work descriptor can be processed in parallel with one or more other work descriptors, and an address field associated with the one or more operations and to store the work descriptor to a work queue.