公开(公告)号：EP4128350A1

公开(公告)日：2023-02-08

申请号：EP20927767.2

申请日：2020-12-23

申请人： INTEL Corporation

发明人： SHARMA, Abhishek ,  SATO, Noriyuki ,  ATANASOV, Sarah ,  SUMBUL, Huseyin Ekin ,  CHEN, Gregory K. ,  KNAG, Phil ,  KRISHNAMURTHY, Ram ,  YOO, Hui Jae ,  LE, Van H.

IPC分类号： H01L27/108 ,  H01L27/12 ,  G11C11/4096

公开(公告)号：EP3828775A1

公开(公告)日：2021-06-02

申请号：EP20197345.0

申请日：2020-09-22

申请人： INTEL Corporation

发明人： KNAG, Phil ,  CHEN, Gregory K. ,  KUMAR, Raghavan ,  SUMBUL, Huseyin ,  KRISHNAMURTHY, Ram

IPC分类号： G06N3/04 ,  G06N3/063

摘要： A compute near memory binary neural network accelerator with digital circuits that achieves energy efficiencies comparable to or surpassing a compute near memory binary neural network accelerator with analog circuits is provided. The compute near memory binary neural network accelerator with digital circuits is more process scalable, robust to process, voltage and temperature variations, and immune to circuit noise.

公开(公告)号：EP3686814A1

公开(公告)日：2020-07-29

申请号：EP19199361.7

申请日：2019-09-24

申请人： INTEL Corporation

发明人： YOUNG, Ian ,  KRISHNAMURTHY, Ram ,  NIKONOV, Dmitri ,  MANIPATRUNI, Sasikanth ,  MATHURIYA, Amrita

IPC分类号： G06N3/063 ,  G06N3/04

摘要： Techniques are provided for implementing a hybrid processing architecture comprising a general-purpose processor (CPU) coupled to an analog in-memory artificial intelligence (AI) processor. A hybrid processor implementing the techniques according to an embodiment includes an AI processor configured to perform analog in-memory computations based on neural network (NN) weighting factors and input data provided by the CPU. The AI processor includes one or more NN layers. The NN layers include digital access circuits to receive data and weighting factors and to provide computational results. The NN layers also include memory circuits to store data and weights, and further include bit line processors and cross bit line processors to perform analog dot product computations between columns of the data memory circuits and the weight factor memory circuits. Some of the NN layers are configured as convolutional NN layers and others are configured as fully connected NN layers, according to some embodiments.

公开(公告)号：EP2798429A1

公开(公告)日：2014-11-05

申请号：EP11878976.7

申请日：2011-12-30

申请人： Intel Corporation

发明人： AGARWAL, Amit ,  HSU, Steven ,  KRISHNAMURTHY, Ram

IPC分类号： G06F1/00 ,  G06F13/14 ,  G06F9/06

CPC分类号： G06F9/30032 ,  G06F9/30036

摘要： Disclosed is a system and device and related methods for data manipulation, especially for SIMD operations such as permute, shift, and rotate. An apparatus includes a permute section that repositions data on sub-word boundaries and a shift section that repositions the data distances smaller than the sub-word width. The sub-word width is configurable and selectable, and the permute section and shift section may operate on different boundary widths. In a first stage, the permute section repositions the data at the nearest sub-word boundary and, in a second stage, the shift section repositions the data to its final desired position. The shift section includes multi-stages set in a logarithmic cascade relationship. Additionally, each shifter within each of the multi-stages is highly connected, allowing fast and precise data movements.

公开(公告)号：EP4109236A1

公开(公告)日：2022-12-28

申请号：EP22164550.0

申请日：2022-03-25

申请人： INTEL Corporation

发明人： KRISHNAMURTHY, Ram ,  ANDERS, Mark ,  KAUL, Himanshu ,  CHINYA, Gautham ,  POWER, Martin ,  MOHAPATRA, Debabrata ,  RAHA, Arnab ,  LANGHAMMER, Martin ,  BRICK, Cormac

IPC分类号： G06F7/53

摘要： Systems, apparatuses and methods may provide for multi-precision multiply-accumulate (MAC) technology that includes a plurality of arithmetic blocks, wherein the plurality of arithmetic blocks each contain multiple multipliers, and wherein the logic is to combine multipliers one or more of within each arithmetic block or across multiple arithmetic blocks. In one example, one or more intermediate multipliers are of a size that is less than precisions supported by arithmetic blocks containing the one or more intermediate multipliers.

公开(公告)号：EP3857463A1

公开(公告)日：2021-08-04

申请号：EP19866783.4

申请日：2019-08-22

申请人： Intel Corporation

发明人： SHARMA, Abhishek ,  KAVALIEROS, Jack T. ,  YOUNG, Ian A. ,  KRISHNAMURTHY, Ram ,  MANIPATRUNI, Sasikanth ,  AVCI, Uygar ,  CHEN, Gregory K. ,  MATHURIYA, Amrita ,  KUMAR, Raghavan ,  KNAG, Phil ,  SUMBUL, Huseyin Ekin ,  HARATIPOUR, Nazila ,  LE, Van H.

IPC分类号： G06N3/063 ,  H01L27/108 ,  G11C11/409 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11

公开(公告)号：EP3504794A1

公开(公告)日：2019-07-03

申请号：EP17844081.4

申请日：2017-07-21

申请人： INTEL Corporation

发明人： AGARWAL, Amit ,  HSU, Steven ,  REALOV, Simeon ,  KRISHNAMURTHY, Ram

IPC分类号： H03K3/037 ,  H03K3/356

公开(公告)号：EP3042304A1

公开(公告)日：2016-07-13

申请号：EP13893029.2

申请日：2013-09-06

申请人： Intel Corporation

发明人： ANDERS, Mark ,  CHEN, Gregory ,  KAUL, Himanshu ,  KRISHNAMURTHY, Ram ,  BORKAR, Shekhar

IPC分类号： G06F15/76 ,  G06F1/32

CPC分类号： H04L12/6418 ,  G06F15/7825 ,  H04L49/109 ,  H04L49/251 ,  H04L49/252 ,  H04L49/9042

摘要： Techniques and mechanisms for performing circuit-switched routing and packet-switched routing for network communication. In an embodiment, a router evaluates control information of a packet received by the router, the evaluation to detect whether the packet includes data for a sideband communication. Based on the evaluation, the router performs a selection from among a plurality of modes of the router, the plurality of modes including a first mode to route the packet for packet-switched communication of sideband data in a network. The plurality of modes also includes a second mode to configure a circuit-switched channel according to the packet. In another embodiment, the router determines a direction for routing a packet in a hierarchical network, wherein the determining of the direction is based on a level of the router in a hierarchy of the hierarchical network.