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公开(公告)号：EP3828717A3
公开(公告)日：2021-06-09
申请号：EP21153098.5
申请日：2013-12-26
申请人： INTEL Corporation
发明人： WU, Zuoguo J. , WAGH, Mahesh , DAS SHARMA, Debendra , PASDAST, Gerald S. , AYYASAMY, Ananthan , LI, Xiaobei , BLANKENSHIP, Robert G. , SAFRANEK, Robert J.
摘要： Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
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2.发明公开CROSS-DIE INTERFACE SNOOP OR GLOBAL OBSERVATION MESSAGE ORDERING 审中-公开交叉接口（CDI）SNOOP ODER GLOBALE BEOBACHTUNGSNACHRICHTENANORDNUNG
公开(公告)号：EP3037972A1
公开(公告)日：2016-06-29
申请号：EP15195503.6
申请日：2015-11-19
申请人： Intel Corporation
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0833 , G06F2212/621 , Y02D10/13
摘要： Methods and apparatus relating to techniques for Cross-Die Interface (CDI) snoop and/or go (or completion) message ordering are described. In one embodiment, the order of a snoop message and a completion message are determined based at least on status of two bits. The snoop and completion messages are exchanged between a first integrated circuit die and a second integrated circuit die. The first integrated circuit die and the second integrated circuit die are coupled through a first interface and a second interface and the snoop message and the completion message are exchanged over at least one of the first interface and the second interface. Other embodiments are also disclosed.
摘要翻译： 描述与跨模接口（CDI）窥探和/或去（或完成）消息排序技术有关的方法和装置。 在一个实施例中，至少基于两位的状态来确定窥探消息和完成消息的顺序。 窥探和完成消息在第一集成电路管芯和第二集成电路管芯之间交换。 第一集成电路管芯和第二集成电路管芯通过第一接口和第二接口耦合，并且窥探消息和完成消息通过第一接口和第二接口中的至少一个进行交换。 还公开了其它实施例。
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公开(公告)号：EP2909728A1
公开(公告)日：2015-08-26
申请号：EP13848818.4
申请日：2013-03-16
申请人： Intel Corporation
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on cach of the lanes.
摘要翻译： 事务处理数据被识别，并且生成微片以包括三个或更多个插槽以及用作两个或更多个插槽中的任何一个插槽的扩展的浮动字段。 至少部分地基于三个或更多个时隙，将所述微片通过串行数据链路发送到用于处理的设备。
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公开(公告)号：EP3087491B1
公开(公告)日：2018-12-05
申请号：EP13900085.5
申请日：2013-12-26
申请人： Intel Corporation
发明人： WU, Zuoguo J. , WAGH, Mahesh , DAS SHARMA, Debendra , PASDAST, Gerald S. , AYYASAMY, Ananthan , LI, Xiaobei , BLANKENSHIP, Robert G. , SAFRANEK, Robert J.
CPC分类号： G06F13/4022 , G06F1/10 , G06F13/124 , G06F13/4273 , G06F13/4282 , G06F15/173 , Y02D10/14 , Y02D10/151
摘要： Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
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公开(公告)号：EP3087491A1
公开(公告)日：2016-11-02
申请号：EP13900085.5
申请日：2013-12-26
申请人： Intel Corporation
发明人： WU, Zuoguo J. , WAGH, Mahesh , DAS SHARMA, Debendra , PASDAST, Gerald S. , AYYASAMY, Ananthan , LI, Xiaobei , BLANKENSHIP, Robert G. , SAFRANEK, Robert J.
CPC分类号： G06F13/4022 , G06F1/10 , G06F13/124 , G06F13/4273 , G06F13/4282 , G06F15/173 , Y02D10/14 , Y02D10/151
摘要： Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
摘要翻译： 物理层逻辑被提供用于在物理链路的一个或多个数据通道上接收数据，在物理链路的另一个通道上接收一个有效信号，该有效信号标识该有效数据将跟随有效信号在一个或 更多的数据通道，并且在物理链路的另一个通道上接收标识在一个或多个数据通道上的数据类型的流信号。
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公开(公告)号：EP3828717A2
公开(公告)日：2021-06-02
申请号：EP21153098.5
申请日：2013-12-26
申请人： INTEL Corporation
发明人： WU, Zuoguo J. , WAGH, Mahesh , DAS SHARMA, Debendra , PASDAST, Gerald S. , AYYASAMY, Ananthan , LI, Xiaobei , BLANKENSHIP, Robert G. , SAFRANEK, Robert J.
摘要： Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
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公开(公告)号：EP3361391A1
公开(公告)日：2018-08-15
申请号：EP18165258.7
申请日：2013-12-26
申请人： INTEL Corporation
发明人： WU, Zuoguo J. , WAGH, Mahesh , DAS SHARMA, Debendra , PASDAST, Gerald S. , AYYASAMY, Ananthan , LI, Xiaobei , BLANKENSHIP, Robert G. , SAFRANEK, Robert J.
IPC分类号： G06F13/42
CPC分类号： G06F13/4022 , G06F1/10 , G06F13/124 , G06F13/4273 , G06F13/4282 , G06F15/173 , Y02D10/14 , Y02D10/151
摘要： Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
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