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公开(公告)号：EP0422391A3
公开(公告)日：1991-07-03
申请号：EP90117239.5
申请日：1990-09-07
IPC分类号： H03K19/0185 , H03K19/003 , H03K19/017
CPC分类号： H03K19/00361 , H03K19/01721
摘要： A CMOS integrated circuit for driving capacitance has an input node (10) and an output node (20) and includes a first transistor (14) operatively connected to the input node (10) which is turned "on" and "off" by the input node (10) to supply an output signal to the output node (20) when turned "on". A second transistor (24) is provided, the output of which is connected to the output node (20) when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor (14) prior to the second transistor (24), and to turn on the second transistor (24) if and only if the slew rate of the output signal of the first transistor (14) is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor (14) will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor (24); however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor (14) will cause the second transistor (24) to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.
摘要翻译： 用于驱动电容的CMOS集成电路具有输入节点（10）和输出节点（20），并且包括可操作地连接到输入节点（10）的第一晶体管（14），所述输入节点（10）被所述输入节点 输入节点（10），当输入节点（10）被打开时向输出节点（20）提供输出信号。 提供第二晶体管（24），当第二晶体管（24）接通时，其输出端连接到输出节点（20）以向其输出信号。 提供控制电路以在第二晶体管（24）之前接通第一晶体管（14），并且当且仅当第一晶体管（14）的输出信号的转换速率 ）比给定值少或慢。 通过这种布置，如果驱动电容器件的总电容较小，则第一晶体管（14）将具有足够快的转换速率，其将在不接通第二晶体管（24）的情况下执行器件的整个充电功能 ）; 然而，如果被充电的器件的总电容足够大，则第一晶体管（14）的低压摆率将导致第二晶体管（24）导通，从而为电容器件提供额外的充电电压，因此 减少仅在整个充电中采用第一晶体管时所需的时间。
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2.发明公开
公开(公告)号：EP0442301A3
公开(公告)日：1993-04-07
申请号：EP91100883.7
申请日：1991-01-24
发明人： Barth, John Edward, Jr. , Drake, Charles Edward , Fifield, John Atkinson , Hovis, William Paul , Kalter, Howard Leo , Lewis, Scott Clarence , Nickel, Daniel John , Stapper, Charles Henri , Yankosky, James Andrew
CPC分类号： G11C29/84 , G06F11/1008
摘要： A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.
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3.发明授权Dynamic RAM with on-chip ECC and optimized bit and word redundancy 失效带有片上错误检查和纠正和optimisierender位及冗余动态RAM
公开(公告)号：EP0442301B1
公开(公告)日：1996-12-04
申请号：EP91100883.7
申请日：1991-01-24
发明人： Barth, John Edward, Jr. , Drake, Charles Edward , Fifield, John Atkinson , Hovis, William Paul , Kalter, Howard Leo , Lewis, Scott Clarence , Nickel, Daniel John , Stapper, Charles Henri , Yankosky, James Andrew
CPC分类号： G11C29/84 , G06F11/1008
摘要： A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.
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公开(公告)号：EP0442283A3
公开(公告)日：1992-10-28
申请号：EP91100624.5
申请日：1991-01-19
发明人： Barth, John Edward, Jr. , Drake, Charles Edward , Hovis, William Paul , Kalter, Howard Leo , Kelley, Gordon Arthur, Jr. , Lewis, Scott Clarence , Nickel, Daniel John , Yankosky, James Andrew
IPC分类号： G11C8/00
摘要： Low power addressing systems are provided which include a given number of memory segments (26, 28, 30, 32, 34, 38), each having word and bit/sense lines, a given number of decoders (42, 44, 46, 48, 50, 52, 54, 56) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one word line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a first plurality of transmission gate systems (58, 60, 62, 64), each having first (92) and second (94) transmission gates, with each of the gates being coupled to a different one of the decoders (42, 44, 46, 48, 50, 52, 56), a second decoder (66) having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems (58, 60, 62, 64), first control circuits for selectively activating the first (92) and second (94) gates in each of the first plurality of transmission gate systems (58, 60, 62, 64), a third given number of decoders (68, 70, 72, 74, 76, 80, 82) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one bit/sense line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a second plurality of transmission gate systems (84, 86, 88, 90), each having first (102) and second (104) transmission gates, with each of the gates of the second plurality of transmission gate systems (84, 86, 88, 90) being coupled to a different one of the third given number of decoders (26, 28, 30, 32, 34, 36, 38), and second control circuits for selectively activating the first (102) and second (104) gates of each of the third plurality of transmission gate systems (26, 28, 30, 32, 34, 36, 38).
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5.发明公开Dynamic RAM with on-chip ECC and optimized bit and word redundancy 失效Dynamischer RAM mit On-Chip-Fehlerprüfung-und -korrektur und mit optimisierender Bit- und Wortredundanz。
公开(公告)号：EP0442301A2
公开(公告)日：1991-08-21
申请号：EP91100883.7
申请日：1991-01-24
发明人： Barth, John Edward, Jr. , Drake, Charles Edward , Fifield, John Atkinson , Hovis, William Paul , Kalter, Howard Leo , Lewis, Scott Clarence , Nickel, Daniel John , Stapper, Charles Henri , Yankosky, James Andrew
CPC分类号： G11C29/84 , G06F11/1008
摘要： A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.
摘要翻译： 具有片上ECC（30）以及已经优化以支持片上ECC的位和字冗余的DRAM。 位线冗余具有交换网络，为相关联的存储器阵列中的位线提供任意替代。 字线冗余在单独的阵列部分（20）中提供，并且已被优化以最大化信号，同时减少软错误。 阵列以每个字线上的纠错字（ECW）的形式存储数据。 第一组数据线（以锯齿形图案形成以最小化底层位线上的不平等电容负载）被耦合以读出ECW以及冗余位线。 第二组数据线通过位线冗余校正ECW，并且第三组数据线接收由字线冗余校正的ECW。 第三组数据线耦合到ECC块，其校正ECW中遇到的错误。 ECC电路（30）被优化以通过执行片上纠错来减少引入的访问延迟。 ECC块（30）将校正的数据位和校验位都提供给SRAM（40）。 因此，校验位可以被外部访问，从而提高存储芯片的可测试性。 同时，当使用多位访问模式时，在SRAM（40）中具有一组相关位改善了访问性能，这补偿了由ECC引入的任何访问延迟。 为了最大化从模式切换到模式的效率，将模式设置为接收到的地址信号的函数。
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公开(公告)号：EP0442283B1
公开(公告)日：1996-05-08
申请号：EP91100624.5
申请日：1991-01-19
发明人： Barth, John Edward, Jr. , Drake, Charles Edward , Hovis, William Paul , Kalter, Howard Leo , Kelley, Gordon Arthur, Jr. , Lewis, Scott Clarence , Nickel, Daniel John , Yankosky, James Andrew
IPC分类号： G11C8/00
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公开(公告)号：EP0422391B1
公开(公告)日：1995-05-24
申请号：EP90117239.5
申请日：1990-09-07
IPC分类号： H03K19/0185 , H03K19/003 , H03K19/017
CPC分类号： H03K19/00361 , H03K19/01721
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公开(公告)号：EP0442283A2
公开(公告)日：1991-08-21
申请号：EP91100624.5
申请日：1991-01-19
发明人： Barth, John Edward, Jr. , Drake, Charles Edward , Hovis, William Paul , Kalter, Howard Leo , Kelley, Gordon Arthur, Jr. , Lewis, Scott Clarence , Nickel, Daniel John , Yankosky, James Andrew
IPC分类号： G11C8/00
摘要： Low power addressing systems are provided which include a given number of memory segments (26, 28, 30, 32, 34, 38), each having word and bit/sense lines, a given number of decoders (42, 44, 46, 48, 50, 52, 54, 56) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one word line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a first plurality of transmission gate systems (58, 60, 62, 64), each having first (92) and second (94) transmission gates, with each of the gates being coupled to a different one of the decoders (42, 44, 46, 48, 50, 52, 56), a second decoder (66) having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems (58, 60, 62, 64), first control circuits for selectively activating the first (92) and second (94) gates in each of the first plurality of transmission gate systems (58, 60, 62, 64), a third given number of decoders (68, 70, 72, 74, 76, 80, 82) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one bit/sense line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a second plurality of transmission gate systems (84, 86, 88, 90), each having first (102) and second (104) transmission gates, with each of the gates of the second plurality of transmission gate systems (84, 86, 88, 90) being coupled to a different one of the third given number of decoders (26, 28, 30, 32, 34, 36, 38), and second control circuits for selectively activating the first (102) and second (104) gates of each of the third plurality of transmission gate systems (26, 28, 30, 32, 34, 36, 38).
摘要翻译： 提供了低功率寻址系统，其包括给定数量的存储器段（26,28,30,32,34,38），每个存储器段具有字和位/检测线，给定数量的解码器（42,44,46,48） ，50,52,54,56），其耦合到所述给定数量的存储器段（26,28,30,32,34,36,38），用于选择每个所述存储器段（26,28,30,36,36,38）中的一个字线， 32,34,36,38），第一多个传输门系统（58,60,62,64），每个具有第一（92）和第二（94）传输门，其中每个栅极耦合到不同的 解码器之一（42,44,46,48,50,52,56），具有第一多个输出的第二解码器（66），每个输出耦合到相应的一个传输门系统（58 ，60,62,64），用于选择性地激活第一多个传输门系统（58,60,62,64）中的每一个中的第一（92）和第二（94）门的第一控制电路，第三给定数量 解码器（68,70,72,74,76,80,82） 上升到给定数量的存储器段（26,28,30,32,34,36,38），用于选择每个存储器段（26,28,30,32,34,36,38）中的一个位/感测线 ），第二多个传输门系统（84,86,88,90），每个具有第一（102）和第二（104）传输门，其中第二多个传输门系统的每个栅极（84,86 ，88，90）耦合到所述第三给定数量的解码器（26,28,30,32,34,36,38）中的不同的一个，以及用于选择性地激活所述第一（102）和第二（104） ）第三多个传输门系统（26,28,30,32,34,36,38）中的每一个的门。
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公开(公告)号：EP0422391A2
公开(公告)日：1991-04-17
申请号：EP90117239.5
申请日：1990-09-07
IPC分类号： H03K19/0185 , H03K19/003 , H03K19/017
CPC分类号： H03K19/00361 , H03K19/01721
摘要： A CMOS integrated circuit for driving capacitance has an input node (10) and an output node (20) and includes a first transistor (14) operatively connected to the input node (10) which is turned "on" and "off" by the input node (10) to supply an output signal to the output node (20) when turned "on". A second transistor (24) is provided, the output of which is connected to the output node (20) when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor (14) prior to the second transistor (24), and to turn on the second transistor (24) if and only if the slew rate of the output signal of the first transistor (14) is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor (14) will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor (24); however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor (14) will cause the second transistor (24) to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.
摘要翻译： 用于驱动电容的CMOS集成电路具有输入节点（10）和输出节点（20），并且包括可操作地连接到输入节点（10）的第一晶体管（14），所述输入节点（10）被所述输入节点 输入节点（10），当输入节点（10）被打开时向输出节点（20）提供输出信号。 提供第二晶体管（24），当第二晶体管（24）接通时，其输出端连接到输出节点（20）以向其输出信号。 提供控制电路以在第二晶体管（24）之前接通第一晶体管（14），并且当且仅当第一晶体管（14）的输出信号的转换速率 ）比给定值少或慢。 通过这种布置，如果驱动电容器件的总电容较小，则第一晶体管（14）将具有足够快的转换速率，其将在不接通第二晶体管（24）的情况下执行器件的整个充电功能 ）; 然而，如果被充电的器件的总电容足够大，则第一晶体管（14）的低压摆率将导致第二晶体管（24）导通，从而为电容器件提供额外的充电电压，因此 减少仅在整个充电中采用第一晶体管时所需的时间。
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