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公开(公告)号：EP0393347A2
公开(公告)日：1990-10-24
申请号：EP90104690.4
申请日：1990-03-13
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C11/4097 , G11C7/18
摘要： This invention relates to semiconductor memories and includes a sense amplifier architecture in which sensed data bit lines (e.g. BL2, BL2′) are electrically isolated and shielded from their immediately adjacent active neighbors by utilization of non-selected bit lines (e.g. BL1, BL1′ and/or BL3, BL3′) as an AC ground bus. In its simplest embodiment, shielded bit line (SBL) architecture includes two pairs of opposed bit lines (BL1, BL2; BL1′, BL2′)associated with a common sense amplifier (10). One of each of the bit line pairs is multiplexed into the sense amplifier and the other unselected bit line pair is clamped to AC ground to shield the selected bit line pair from all dynamic line-to-line coupling.
摘要翻译： 本发明涉及半导体存储器，并且包括读出放大器架构，其中感测数据位线（例如BL2，BL2min）通过利用未选择的位线（例如BL1，BL1min）被电隔离并与其紧邻的有源邻居屏蔽 和/或BL3，BL3分钟）作为交流接地总线。 在其最简单的实施例中，屏蔽位线（SBL）架构包括与公共读出放大器（10）相关联的两对相对的位线（BL1，BL2; BL1min，BL2min）。 每个位线对中的一个被复用到读出放大器中，而另一个未选择的位线对被钳位到AC地，以将所选择的位线对与所有动态线对线耦合屏蔽。
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公开(公告)号：EP0096225A2
公开(公告)日：1983-12-21
申请号：EP83104486.2
申请日：1983-05-06
IPC分类号： H03K19/177 , G06F7/50
CPC分类号： G06F7/5057 , H03K19/096 , H03K19/1772
摘要： A programmable PLA circuit in which an interlaced AND/OR array (30, 32, 34) is provided which has both common input (16) and common output lines (36). Separate AND and OR functions are generated during two different timing intervals (D1, D2) such that both of the logical arrays can physically share input and output circuit elements. A binary adder is described in which pairs of array output lines are applied to the same Exclusive-NOR circuits (40) during the two time intervals to provide the Exclusive-NOR of product terms during the AND array time interval (D1) and to provide the Exclusive-NOR of sums of product terms or the sum of the Exclusive-NOR of product terms during the second time interval (D2).
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公开(公告)号：EP0055803A3
公开(公告)日：1983-11-09
申请号：EP81108551
申请日：1981-10-20
CPC分类号： G11C16/0433
摘要： A memory system, particularly an electrically alterable read only memory system which includes a semiconductor substrate (10) having a diffusion region (12) therein defining one end of a channel region (14), a control plate (22, T1), a floating plate (20) separated from the channel region by a thin dielectric layer (16) and disposed between the control plate (22) and the channel region (14) and means (T1-T3) for transferring charge to and from the floating plate (22). A control gate (32) is coupled to the channel region (14) and is located between the diffusion region (12) and the floating plate (22). The control gate (32) may be connected to a word line and the diffusion region (12) may be connected to a bit/sense line. The channel region (14) is controlled by the word line and the presence or absence of charge on the floating plate (20). Thus, information may be read from a cell of the memory by detecting the presence or absence of charge stored in the inversion capacitor under the floating plate (20). The charge transfer means (T1-T3) includes an enhanced conduction insulator (24) and means (T1, T3) for applying appropriate voltages to the control plate (22) and to the control gate (32) to transfer charge to and from the floating plate (20) through the enhanced conduction insulator (24).
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4.发明授权Dynamic RAM with on-chip ECC and optimized bit and word redundancy 失效带有片上错误检查和纠正和optimisierender位及冗余动态RAM
公开(公告)号：EP0442301B1
公开(公告)日：1996-12-04
申请号：EP91100883.7
申请日：1991-01-24
发明人： Barth, John Edward, Jr. , Drake, Charles Edward , Fifield, John Atkinson , Hovis, William Paul , Kalter, Howard Leo , Lewis, Scott Clarence , Nickel, Daniel John , Stapper, Charles Henri , Yankosky, James Andrew
CPC分类号： G11C29/84 , G06F11/1008
摘要： A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.
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公开(公告)号：EP0386462B1
公开(公告)日：1996-05-01
申请号：EP90102079.2
申请日：1990-02-02
发明人： Blake, Robert Martin , Bossen, Douglas Craig , Chen, Chin-Long , Fifield, John Atkinson , Kalter, Howard Leo , Lo, Tin-Chee
IPC分类号： G06F11/00
CPC分类号： G06F11/1052 , G06F11/1008
摘要： In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：EP0442283A3
公开(公告)日：1992-10-28
申请号：EP91100624.5
申请日：1991-01-19
发明人： Barth, John Edward, Jr. , Drake, Charles Edward , Hovis, William Paul , Kalter, Howard Leo , Kelley, Gordon Arthur, Jr. , Lewis, Scott Clarence , Nickel, Daniel John , Yankosky, James Andrew
IPC分类号： G11C8/00
摘要： Low power addressing systems are provided which include a given number of memory segments (26, 28, 30, 32, 34, 38), each having word and bit/sense lines, a given number of decoders (42, 44, 46, 48, 50, 52, 54, 56) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one word line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a first plurality of transmission gate systems (58, 60, 62, 64), each having first (92) and second (94) transmission gates, with each of the gates being coupled to a different one of the decoders (42, 44, 46, 48, 50, 52, 56), a second decoder (66) having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems (58, 60, 62, 64), first control circuits for selectively activating the first (92) and second (94) gates in each of the first plurality of transmission gate systems (58, 60, 62, 64), a third given number of decoders (68, 70, 72, 74, 76, 80, 82) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one bit/sense line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a second plurality of transmission gate systems (84, 86, 88, 90), each having first (102) and second (104) transmission gates, with each of the gates of the second plurality of transmission gate systems (84, 86, 88, 90) being coupled to a different one of the third given number of decoders (26, 28, 30, 32, 34, 36, 38), and second control circuits for selectively activating the first (102) and second (104) gates of each of the third plurality of transmission gate systems (26, 28, 30, 32, 34, 36, 38).
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7.发明公开Dynamic RAM with on-chip ECC and optimized bit and word redundancy 失效Dynamischer RAM mit On-Chip-Fehlerprüfung-und -korrektur und mit optimisierender Bit- und Wortredundanz。
公开(公告)号：EP0442301A2
公开(公告)日：1991-08-21
申请号：EP91100883.7
申请日：1991-01-24
发明人： Barth, John Edward, Jr. , Drake, Charles Edward , Fifield, John Atkinson , Hovis, William Paul , Kalter, Howard Leo , Lewis, Scott Clarence , Nickel, Daniel John , Stapper, Charles Henri , Yankosky, James Andrew
CPC分类号： G11C29/84 , G06F11/1008
摘要： A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.
摘要翻译： 具有片上ECC（30）以及已经优化以支持片上ECC的位和字冗余的DRAM。 位线冗余具有交换网络，为相关联的存储器阵列中的位线提供任意替代。 字线冗余在单独的阵列部分（20）中提供，并且已被优化以最大化信号，同时减少软错误。 阵列以每个字线上的纠错字（ECW）的形式存储数据。 第一组数据线（以锯齿形图案形成以最小化底层位线上的不平等电容负载）被耦合以读出ECW以及冗余位线。 第二组数据线通过位线冗余校正ECW，并且第三组数据线接收由字线冗余校正的ECW。 第三组数据线耦合到ECC块，其校正ECW中遇到的错误。 ECC电路（30）被优化以通过执行片上纠错来减少引入的访问延迟。 ECC块（30）将校正的数据位和校验位都提供给SRAM（40）。 因此，校验位可以被外部访问，从而提高存储芯片的可测试性。 同时，当使用多位访问模式时，在SRAM（40）中具有一组相关位改善了访问性能，这补偿了由ECC引入的任何访问延迟。 为了最大化从模式切换到模式的效率，将模式设置为接收到的地址信号的函数。
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8.发明公开Fault tolerant computer memory system with disablement feature 失效Fehlertolerantes Rechnerspeichersystem mitUnfähigkeitscharakteristikum。
公开(公告)号：EP0386461A2
公开(公告)日：1990-09-12
申请号：EP90102078.4
申请日：1990-02-02
发明人： Blake, Robert Martin , Bossen, Douglas Craig , Chen, Chin-Long , Fifield, John Atkinson , Kalter, Howard Leo
IPC分类号： G06F11/00
CPC分类号： G06F11/1052 , G06F11/1008
摘要： In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
摘要翻译： 在包括多个存储单元（10）的存储器系统中，每个存储器单元具有单位级错误校正能力（20），并且每个存储器单元都连接到系统级错误校正功能（30），通过提供装置 （图2），用于例如响应于在一个存储器单元中出现不可校正的错误来禁用单元级纠错能力。 这种禁用纠错功能的反直觉方法仍然提高了整体存储系统的可靠性，因为它可以使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。 因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。
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公开(公告)号：EP0096225A3
公开(公告)日：1985-03-20
申请号：EP83104486
申请日：1983-05-06
IPC分类号： H03K19/177 , G06F07/50
CPC分类号： G06F7/5057 , H03K19/096 , H03K19/1772
摘要： A programmable PLA circuit in which an interlaced AND/OR array (30, 32, 34) is provided which has both common input (16) and common output lines (36). Separate AND and OR functions are generated during two different timing intervals (D1, D2) such that both of the logical arrays can physically share input and output circuit elements. A binary adder is described in which pairs of array output lines are applied to the same Exclusive-NOR circuits (40) during the two time intervals to provide the Exclusive-NOR of product terms during the AND array time interval (D1) and to provide the Exclusive-NOR of sums of product terms or the sum of the Exclusive-NOR of product terms during the second time interval (D2).
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10.发明授权Fault tolerant computer memory system with disablement feature 失效容错计算机存储器系统，与Entvalidierungsmerkmal。
公开(公告)号：EP0386461B1
公开(公告)日：1995-08-09
申请号：EP90102078.4
申请日：1990-02-02
发明人： Blake, Robert Martin , Bossen, Douglas Craig , Chen, Chin-Long , Fifield, John Atkinson , Kalter, Howard Leo
IPC分类号： G06F11/00
CPC分类号： G06F11/1052 , G06F11/1008
摘要： In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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