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公开(公告)号：EP0192121B1
公开(公告)日：1992-04-29
申请号：EP86101471.0
申请日：1986-02-05
IPC分类号： G11C29/00
CPC分类号： G11C29/50016 , G06F2201/81 , G11C29/50
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2.发明公开Boosted drive system for master/local word line memory architecture 失效Antriebsverstärkersystemfürmit Haupt- / Nebenwortleitungen ausgestatteten Speicher。
公开(公告)号：EP0551598A2
公开(公告)日：1993-07-21
申请号：EP92120275.0
申请日：1992-11-27
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： An integrated boost and local word line drive system that enhances the speed of the word line drive without providing excessive voltage stresses to the driver devices. A charge reservoir (20) stores a boost voltage (BST) under the control of a charge pump (15) that is regulated by a voltage regulator (10). One of the local word lines (LWL) coupled to a selected master word line (MWL) is enabled by a driver (50) that receives the boost voltage (BST). The switching times and signal slew rates of the driver, as well as the boost voltage, are controlled to prevent excessive gate stresses in the support circuitry.
摘要翻译： 集成升压和本地字线驱动系统，可提高字线驱动的速度，而不会对驱动器设备造成过大的电压应力。 电荷贮存器（20）在由电压调节器（10）调节的电荷泵（15）的控制下存储升压电压（BST）。 耦合到所选主字线（MWL）的一个本地字线（LWL）由接收升压电压（BST）的驱动器（50）使能。 控制驱动器的切换时间和信号转换速率以及升压电压，以防止支持电路中的过大的栅极应力。
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公开(公告)号：EP0192121A2
公开(公告)日：1986-08-27
申请号：EP86101471.0
申请日：1986-02-05
IPC分类号： G11C29/00
CPC分类号： G11C29/50016 , G06F2201/81 , G11C29/50
摘要： A test circuit is provided wherein data is stored in circuits or cells of an array or matrix with the use of conventional or normal operating voltages. Voltages at internal nodes of the circuits or cells are altered to magnitudes beyond the normal operating ranges, which includes significantly decreasing the offset voltage, for a short period of time and then the stored data is read out at normal voltages and currents and compared with the data written into the circuits or cells.
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公开(公告)号：EP0551598A3
公开(公告)日：1994-11-09
申请号：EP92120275.0
申请日：1992-11-27
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： An integrated boost and local word line drive system that enhances the speed of the word line drive without providing excessive voltage stresses to the driver devices. A charge reservoir (20) stores a boost voltage (BST) under the control of a charge pump (15) that is regulated by a voltage regulator (10). One of the local word lines (LWL) coupled to a selected master word line (MWL) is enabled by a driver (50) that receives the boost voltage (BST). The switching times and signal slew rates of the driver, as well as the boost voltage, are controlled to prevent excessive gate stresses in the support circuitry.
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公开(公告)号：EP0031030A3
公开(公告)日：1983-04-20
申请号：EP80107149
申请日：1980-11-18
CPC分类号： G11C11/411 , G11C11/403 , G11C11/4067
摘要： This describes a bipolar semiconductor dynamic RAM cell array in which there is provided a plurality of capacitive storage data cells each being coupled to a respective capacitively loaded bit line and to one another through a common word line. A supply means is coupled to the word line for biasing each cell of the array with respect to its respective bit line to cause the bit line capacitance to set the conductive state of each cell so as to set the respective capacitive storage means of each cell to a selected charge state. The rate at which the storage means of any one cell reaches a selected state is a function of the charge state of any cell, and its respective bit line capacitance, positioned between the selected cell and the supply means.
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公开(公告)号：EP0031030A2
公开(公告)日：1981-07-01
申请号：EP80107149.9
申请日：1980-11-18
CPC分类号： G11C11/411 , G11C11/403 , G11C11/4067
摘要： This describes a bipolar semiconductor dynamic RAM cell array in which there is provided a plurality of capacitive storage data cells each being coupled to a respective capacitively loaded bit line and to one another through a common word line. A supply means is coupled to the word line for biasing each cell of the array with respect to its respective bit line to cause the bit line capacitance to set the conductive state of each cell so as to set the respective capacitive storage means of each cell to a selected charge state. The rate at which the storage means of any one cell reaches a selected state is a function of the charge state of any cell, and its respective bit line capacitance, positioned between the selected cell and the supply means.
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公开(公告)号：EP0192121A3
公开(公告)日：1989-02-22
申请号：EP86101471.0
申请日：1986-02-05
IPC分类号： G11C29/00
CPC分类号： G11C29/50016 , G06F2201/81 , G11C29/50
摘要： A test circuit is provided wherein data is stored in circuits or cells of an array or matrix with the use of conventional or normal operating voltages. Voltages at internal nodes of the circuits or cells are altered to magnitudes beyond the normal operating ranges, which includes significantly decreasing the offset voltage, for a short period of time and then the stored data is read out at normal voltages and currents and compared with the data written into the circuits or cells.
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9.发明公开Monolithisch integriertes Treiberschaltungssystem für die Wortleitungen eines Matrixspeichers 失效单片集成驱动电路系统，用于一个矩阵存储器的字线。
公开(公告)号：EP0064188A2
公开(公告)日：1982-11-10
申请号：EP82103173.9
申请日：1982-04-15
IPC分类号： G11C11/40
CPC分类号： G11C11/415
摘要： Bei dem Treiberschaltungssystem enthalten die Wortleitungsschalter (10, 10A) jeweils zwei als Stromverstärker dienende Transistoren (T2, T4), von denen der erste den zweiten steuert. Sämtliche Wortleitungsschalter sind durch eine erste gemeinsame Leitung (A) miteinander und über einen ersten gemeinsamen Widerstand (R A ) mit dem einen Pol (+V) der Betriebsspannungsquelle verbunden. Über eine zweite gemeinsame Leitung (B) und einen zweiten gemeinsamen Widerstand (R B ) sind sie an den anderen Pol der Betriebsspannungsquelle angeschlossen. Die Kapazitäten (C A , C s ) der ersten und zweiten gemeinsamen Leitungen sind durch die daran angeschlossenen Sperrschichtkapazitäten (C1, C2) der beiden Transistoren eines Wortleitungsschalters vergrößert. Bei Auswählen einer Wortleitung fließt daher ein durch das Entladen der Kapazität (C A ) der ersten gemeinsamen Leitung bedingter Überschußstrom (I C2 ) durch den ersten Transistor, welcher Strom in dem zweiten Transistor verstärkt wird und ein schnelles Entladen der ausgewählten Wortleitung (WLB) ermöglicht. Ein Leitendwerden nicht ausgewählter Wortleitungsschalter wird dadurch verhindert, daß das Potential der ersten gemeinsamen Leitung bei Auswahl eines Wortleitungsschalters durch den Entladestrom ihrer Kapazität abgesenkt und das der zweiten gemeinsamen Wortleitung durch Aufladen ihrer Kapazität angehoben wird.
摘要翻译： 在该驱动电路系统，字线开关（10，10A），每个包括两个用作电流放大器晶体管（T2，T4），其中第一个控制第二。 所有字线开关是通过第一公共线（A）至彼此，并且通过连接到操作电压源的一个极（+ V）的第一共用电阻（RA）。 经由第二公共线（B）和第二共用电阻（RB）被连接到工作电压源的另一极。 所述第一和第二公共线的能力（CA，CB）通过结电容（C1，C2）的字线开关的所述两个晶体管的较大的连接到其上。 当选择字线，因此，能够使通过第一晶体管相关的过载电流（IC2）的第一公共线的电容（CA），该电流是在所述第二晶体管和所述选择的字线的快速放电放大的放电（WLB）流动。 导通的非选择字线开关被防止了第一公共线的电位，在一个字线开关的选择是通过它们的容量的放电和所述第二公共字线降低通过其容量的充电上升。
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