公开(公告)号：EP2780912B1

公开(公告)日：2016-10-26

申请号：EP12805813.8

申请日：2012-11-13

Applicant: SanDisk Technologies LLC

Inventor： RAGHU, Deepak

IPC: G11C11/56 ,  G11C16/34 ,  G11C29/52 ,  G11C29/02 ,  G11C29/50 ,  G06F11/10

CPC classification number: G11C16/04 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/3404 ,  G11C16/349 ,  G11C29/025 ,  G11C29/04 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

公开(公告)号：EP2649619B1

公开(公告)日：2016-07-20

申请号：EP11813470.9

申请日：2011-12-12

Applicant: Qualcomm Incorporated

Inventor： SUH, Jungwon

IPC: G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/40626 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4062

公开(公告)号：EP2939239A1

公开(公告)日：2015-11-04

申请号：EP13868489.9

申请日：2013-06-24

Applicant: Intel Corporation

Inventor： SCHOENBORN, Theodore Z. ,  MOZAK, Christopher P.

IPC: G11C11/406 ,  G11C11/402

CPC classification number: G11C7/02 ,  G11C11/40 ,  G11C11/40611 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50016 ,  G11C2211/4062

Abstract: A memory subsystem can test a memory device in situ, testing the performance of the device in the system it is built into during production. Thus, the refresh rate can be adjusted specific to the memory device(s) of a specific system, rather than defaulting to a refresh frequency specified by a standard for the memory device(s). A test component embedded within the host memory subsystem can perform a test and identify specific bits or lines of memory that produce errors when a lower frequency refresh rate is used. The system maps out the identified bits or lines to prevent the bits/lines from being used in runtime of the system. The memory subsystem can then set its refresh rate to an adjusted refresh rate at which a threshold number of errors can be removed by mapping out the bits/lines.

公开(公告)号：EP2779175A3

公开(公告)日：2014-12-31

申请号：EP13174686.9

申请日：2013-07-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung, Chun-Hsiung ,  Kuo, Nai-Ping ,  Chang, Kuen-Long ,  Chen, Ken-Hui ,  Wang, Yu-Chen

IPC: G11C16/34

CPC classification number: G11C16/34 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/349 ,  G11C29/12005 ,  G11C29/50004 ,  G11C29/50016

Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state characterized by a minimum threshold exceeding a selected read bias. A controller includes a stand-by mode, a write mode and a read mode. Retention check logic executes on power-up, or during the stand-by mode, to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.

公开(公告)号：EP2780912A1

公开(公告)日：2014-09-24

申请号：EP12805813.8

申请日：2012-11-13

Applicant: SanDisk Technologies Inc.

Inventor： RAGHU, Deepak

IPC: G11C11/56 ,  G11C16/34 ,  G11C29/52 ,  G11C29/02 ,  G11C29/50 ,  G06F11/10

CPC classification number: G11C16/04 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/3404 ,  G11C16/349 ,  G11C29/025 ,  G11C29/04 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Data, normally read using a page-by page read process, can be recovered from memory cells connected to a broken word line by performing a sequential read process. To determine whether a word line is broken, both a page-by page read process and a sequential read process are performed. The results of both read processes are compared. If the number of mismatches between the two read processes is greater than a threshold, it is concluded that there is a broken word line.

公开(公告)号：EP1388865B1

公开(公告)日：2013-08-28

申请号：EP03016890.0

申请日：2003-07-24

Applicant: Fujitsu Semiconductor Limited

Inventor： Nakagawa, Yuji

IPC: G11C11/406 ,  G11C29/50

CPC classification number: G11C29/50012 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/50 ,  G11C29/50016

公开(公告)号：EP1542237A1

公开(公告)日：2005-06-15

申请号：EP02780005.1

申请日：2002-11-06

Applicant: FUJITSU LIMITED

Inventor： SHINOZAKI, Naoharu, c/o FUJITSU LIMITED ,  KANDA, Tatsuya, c/o FUJITSU LIMITED ,  SATO, Takahiko, c/o FUJITSU LIMITED ,  FUNYU, Akihiro, c/o FUJITSU LIMITED

IPC: G11C11/401

CPC classification number: G11C29/028 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/02 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/0403 ,  G11C2211/4061

Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

Abstract translation: 响应于以预定周期产生的刷新请求输出刷新信号，并且执行刷新操作。 刷新操作在访问请求和刷新请求之间发生冲突时结束。 因此，与访问请求相对应的访问操作可以随着访问时间的减少而提前开始。 通过根据提供访问请求的时间改变刷新操作的结束时间，可以进一步减少访问时间。 由于形成了用于向外部通知刷新操作的状态的测试电路，所以可以在短时间内评估刷新操作的操作余量。 结果，可以减少半导体存储器的开发周期。

公开(公告)号：EP1388865A2

公开(公告)日：2004-02-11

申请号：EP03016890.0

申请日：2003-07-24

Applicant: FUJITSU LIMITED

Inventor： Nakagawa, Yuji

IPC: G11C11/406 ,  G11C29/00

CPC classification number: G11C29/50012 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/50 ,  G11C29/50016

Abstract: Disclosed is a semiconductor memory device which shortens an external access time when there is contention between an external access and an internal access. The semiconductor memory device includes an arbiter (13) which receives a first entry signal for entering a first access mode (external access) and a second entry signal for entering a second access mode (internal access) and determines priority of the first and second access modes in accordance with an order of receipt of the first and second entry signals. The arbiter (13) sequentially generates a first mode trigger signal corresponding to the first entry signal and a second mode trigger signal corresponding to the second entry signal in accordance with the determined priority. The arbiter (13) executes the first access mode by priority over the second access mode when the arbiter is supplied with the first entry signal with a predetermined period after the second access mode has been determined to have priority.

Abstract translation: 公开了一种当存在外部访问和内部访问之间的竞争时缩短外部访问时间的半导体存储器件。 半导体存储器件包括仲裁器（13），其接收用于进入第一访问模式（外部访问）的第一入口信号和用于进入第二访问模式（内部访问）的第二输入信号，并确定第一和第二访问的优先级 根据接收到第一和第二输入信号的顺序进行模式。 仲裁器（13）根据确定的优先顺序产生对应于第一入口信号的第一模式触发信号和对应于第二输入信号的第二模式触发信号。 当仲裁器在第二接入模式被确定为具有优先权之后，在仲裁器被提供有预定时段的第一条目信号时，仲裁器（13）优先执行第二接入模式。

公开(公告)号：EP0929901B1

公开(公告)日：2001-11-28

申请号：EP97945392.5

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WENDELL, Dennis, L.

IPC: G11C29/00 ,  G06F11/24 ,  G11C8/00

CPC classification number: G11C29/026 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit. By utilizing one or more of these features together, several tests of the memory array may be performed, including characterizing the DC transfer function of the memory cells, the standby power of the memory array, the static noise margin of the memory cells, the alpha particle susceptibility of the memory cells as a function of memory cell supply voltage, the offset voltage of bitline sense amplifiers, and others.

公开(公告)号：EP0616335B1

公开(公告)日：2000-03-29

申请号：EP94101897.0

申请日：1994-02-08

Applicant: FUJITSU LIMITED

Inventor： Kumakura, Sinsuke, c/o Fujitsu Limited ,  Yamazaki, Hirokazu, c/o Fujitsu Limited ,  Watanabe, Hisayoshi, c/o Fujitsu Limited ,  Kasa, Yasushi, c/o Fujitsu Limited

IPC: G11C29/00 ,  G11C16/06

CPC classification number: G11C29/021 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3,..., whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.