MR-head having parasitic shield for electrostatic discharge protection
    4.
    发明公开
    MR-head having parasitic shield for electrostatic discharge protection 失效
    MR头具有寄生屏为静电放电保护

    公开(公告)号:EP0747888A3

    公开(公告)日:1997-05-28

    申请号:EP96303733.8

    申请日:1996-05-24

    摘要: A magneto-resistive read head (107) having a "parasitic shield" (124) provides an alternative path for currents associated with sparkovers, thus preventing such currents from damaging the read head (107). The parasitic shield (124) is provided in close proximity to a conventional magnetic shield (113, 115). The electrical potential of parasitic shield (124) is held essentially equal to the electrical potential of the sensor element (111). If charges accumulate on the conventional shield (113, 115), current will flow to the parasitic shield (124) at a lower potential than would be required for current to flow between the conventional shield (113, 115) and the sensor element (111). Alternatively, conductive spark gap devices (203, 206) are electrically coupled to sensor element leads and to each magnetic shield (201, 202). Each spark gap (203, 206) device is brought within very close proximity of the substrate (207) to provide an alternative path for charge that builds up between the sensor element (213) and the substrate (207) to be discharged. The ends of the spark gaps (203, 206) that are brought into close proximity of the substrate are preferably configured with high electric field density inducing structures which reduce the voltage required to cause a sparkover between the spark gap device (203, 206) and the substrate (207).

    MR-head having parasitic shield for electrostatic discharge protection
    5.
    发明公开
    MR-head having parasitic shield for electrostatic discharge protection 失效
    MR-Kopf mitparasitäremSchirmfürelektrostatischen Entladungsschutz

    公开(公告)号:EP0747888A2

    公开(公告)日:1996-12-11

    申请号:EP96303733.8

    申请日:1996-05-24

    摘要: A magneto-resistive read head (107) having a "parasitic shield" (124) provides an alternative path for currents associated with sparkovers, thus preventing such currents from damaging the read head (107). The parasitic shield (124) is provided in close proximity to a conventional magnetic shield (113, 115). The electrical potential of parasitic shield (124) is held essentially equal to the electrical potential of the sensor element (111). If charges accumulate on the conventional shield (113, 115), current will flow to the parasitic shield (124) at a lower potential than would be required for current to flow between the conventional shield (113, 115) and the sensor element (111). Alternatively, conductive spark gap devices (203, 206) are electrically coupled to sensor element leads and to each magnetic shield (201, 202). Each spark gap (203, 206) device is brought within very close proximity of the substrate (207) to provide an alternative path for charge that builds up between the sensor element (213) and the substrate (207) to be discharged. The ends of the spark gaps (203, 206) that are brought into close proximity of the substrate are preferably configured with high electric field density inducing structures which reduce the voltage required to cause a sparkover between the spark gap device (203, 206) and the substrate (207).

    摘要翻译: 具有“寄生屏蔽”(124)的磁阻式读取头(107)为与火花放电相关的电流提供替代路径,从而防止这种电流损坏读取头(107)。 寄生屏蔽(124)靠近传统的磁屏蔽(113,115)设置。 寄生屏蔽(124)的电势基本上等于传感器元件(111)的电位。 如果电荷累积在常规屏蔽(113,115)上,则电流将以比在常规屏蔽(113,115)和传感器元件(111)之间流动的电流要低的电位流到寄生屏蔽(124) )。 或者,导电火花隙装置(203,206)电耦合到传感器元件引线和每个磁屏蔽(201,202)。 每个火花隙(203,206)装置被带到非常靠近衬底(207)的位置,以提供在传感器元件(213)和衬底(207)之间建立的用于充电的替代路径,以便放电。 靠近衬底的火花隙(203,206)的端部优选地被配置有高电场密度诱导结构,其降低在火花隙装置(203,206)和火花隙装置(203,206)之间引起火花放电所需的电压 基板(207)。

    Trench DRAM cell array
    7.
    发明公开
    Trench DRAM cell array 失效
    沟槽DRAM单元阵列

    公开(公告)号:EP0550894A1

    公开(公告)日:1993-07-14

    申请号:EP92122009.1

    申请日:1992-12-24

    IPC分类号: H01L27/108

    CPC分类号: H01L27/10829

    摘要: A high density substrate plate trench DRAM cell memory device and process are described in which a buried region (32) is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate (10). The buried region (32) is partially formed by ion implantation and diffusion to intersect the walls of the deep trenches (22). The buried region (32) is contacted along its perimeter by a reach through region to complete the isolation. The combined regions reduce charge loss due to better control of device parasitics.

    摘要翻译: 描述了一种高密度衬底板沟槽DRAM单元存储器件和工艺,其中掩埋区域(32)与深沟槽电容器相邻形成,使得DRAM传输FET的衬底区域可以与半导体衬底上的其他FET电隔离 10)。 掩埋区域(32)通过离子注入和扩散部分地形成以与深沟槽(22)的壁相交。 掩埋区域(32)沿其周边与达到的区域接触以完成隔离。 由于更好地控制器件寄生效应,组合区域减少了电荷损失。