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178 条记录 (耗时 0.014 秒)

    DRAM with trench capacitors and logic back-biased transistors integrated on an SOI substrate comprising an intrinsic semiconductor layer and manufacturing method thereof
    6.
    发明公开
    DRAM with trench capacitors and logic back-biased transistors integrated on an SOI substrate comprising an intrinsic semiconductor layer and manufacturing method thereof 审中-公开
    DRAM集成严重电容器和与基材的含本征半导体层的SOI衬底上的偏压提供逻辑晶体管和相应的生产方法

    公开(公告)号：EP2498280A1

    公开(公告)日：2012-09-12

    申请号：EP11290126.9

    申请日：2011-03-11

    申请人： Soitec

    发明人： Daval, Nicolas ,  Aulnette, Cécile ,  Nguyen, Bich-Yen

    IPC分类号： H01L21/334 ,  H01L21/84 ,  H01L27/12 ,  H01L27/108 ,  H01L21/762 ,  H01L21/77 ,  H01L21/20 ,  H01L29/786

    CPC分类号： H01L27/10894 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/66181

    摘要： The present invention relates to a method for the manufacture of a wafer, comprising the steps of providing a doped layer (6) on a semiconductor substrate (5); providing a first intrinsic semiconductor layer (7) on the doped layer; providing a buried oxide layer (9) on the first semiconductor layer; and providing a second semiconductor layer (3) on the buried oxide layer.
    In a first region (A) of the wafer, DRAM devices are formed with capacitor trenches (10) extruding into the doped layer (6).
    In a second region (B) of the wafer, logic TFTs (13) are formed. The first semiconductor layer (7) is doped at locations below the TFTs. These doped regions are provided with contacts (14) for back-biasing the TFTs.

    摘要翻译： 本发明涉及一种用于晶片的制造方法，包括：在（5）的半导体衬底提供掺杂层（6）的工序; 提供所述掺杂层上的第一本征半导体层（7）; 提供所述第一半导体层上的掩埋氧化物层（9）; 以及提供所述掩埋氧化物层上的第二半导体层（3）。 在所述晶片的第一区域（A），DRAM设备被形成为与电容器沟槽（10）挤出到掺杂层（6）。 在所述晶片的第二区域（B），逻辑的TFT（13）形成。 在第一半导体层（7）在所述的TFT下方的位置被掺杂。 设置有触点（14），用于背偏置TFT的这些掺杂区。

    NANOSTRUCTURED MOS CAPACITOR
    7.
    发明公开
    NANOSTRUCTURED MOS CAPACITOR 审中-公开
    NANOSTRUKTURIERTER MOS-KONDENSATOR

    公开(公告)号：EP2289106A1

    公开(公告)日：2011-03-02

    申请号：EP09762766.5

    申请日：2009-06-15

    申请人： QuNano AB

    发明人： WERNERSSON, Lars-Erik

    IPC分类号： H01L29/94 ,  H01L29/06 ,  H01L21/02 ,  H01L21/334 ,  H01L27/08 ,  H01L27/10

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  G11C27/024 ,  H01L27/0808 ,  H01L27/0811 ,  H01L28/40 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/872 ,  H01L29/94 ,  H03B5/1203 ,  H03B5/1228 ,  H03B2200/0042

    摘要： The present invention provides nanostructured MOS capacitor that comprises a nanowire (2) at least partly enclosed by a dielectric layer (5) and a gate electrode (4 ) that encloses at least a portion of the dielectric layer (5). Preferably the nanowire (2) protrudes from a substrate ( 12). The gate electrode (4) defines a gated portion (7) of the nanowire (2), which is allowed to be fully depleted when a first predetermined voltage is applied to the gate electrode (4). A method for providing a variable capacitance in an electronic circuit by using such an nanostructured MOS capacitor is also provided. Thanks to the invention it is possible Io provide a MOS capacitor having an increased capacitance modulation range. It is a further advantage of the invention to provide a MOS capacitor which has relatively low depletion capacitance compared to prior art MOS capacitances.

    Method of making a high-voltage field-effect transistor
    9.
    发明公开
    Method of making a high-voltage field-effect transistor 审中-公开
    制造高压场效应晶体管的方法

    公开(公告)号：EP2264746A3

    公开(公告)日：2011-01-26

    申请号：EP10184211.0

    申请日：2002-08-16

    申请人： Power Integrations, Inc.

    发明人： Disney, Donald, R.

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/40 ,  H01L21/334 ,  H01L29/86 ,  H01L29/417 ,  H01L29/08 ,  H01L29/423

    CPC分类号： H01L29/407 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7828 ,  Y10S438/925

    摘要： A method for fabricating a high-voltage transistor with an extended drain region comprises forming an epitaxial layer (101) on a substrate (100), the epitaxial layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair of spaced-apart trenches that define first and second sidewall portions of the epitaxial layer. A dielectric layer (102) is formed that partially fills each of the trenches, covering the first and second sidewall portions. The remaining portions of the trenches are then filled with a conductive material to form first and second field plate members (103) that are insulated from the substrate and the epitaxial layer. Further trenches (112) are formed in the dielectric layer on opposite sides of the epitaxial layer and gate dielectric layers (116) and gate members (113) are formed within the further trenches.

    摘要翻译： 一种用于制造具有延伸漏极区的高压晶体管的方法包括：在衬底（100）上形成外延层（101），所述外延层和所述衬底为第一导电类型; 然后蚀刻外延层以形成限定外延层的第一和第二侧壁部分的一对间隔开的沟槽。 形成电介质层（102），其部分地填充每个沟槽，覆盖第一和第二侧壁部分。 然后用导电材料填充沟槽的其余部分以形成与衬底和外延层绝缘的第一和第二场板部件（103）。 进一步的沟槽（112）形成在外延层的相对侧上的介电层中，并且栅极介电层（116）和栅极构件（113）形成在另外的沟槽内。