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公开(公告)号：EP1344225B1
公开(公告)日：2005-08-03
申请号：EP01271638.7
申请日：2001-12-04
IPC分类号： G11C29/00
摘要： The invention relates to a circuit arrangement for controlling a programmable connection (1), comprising a volatile memory cell (5), which is coupled to the fuse (1) for permanently memorising the data that is stored in the volatile memory (5) and a shift register (3), which permits data to be read from the volatile memory cell (5) and data to be written to the memory cell (5). To control several fuses (1), several shift registers (3) can be interconnected to form a shift register chain. Said shift register chain (3) enables the rapid reading from and writing to the volatile memory (4), using a circuit of low complexity.
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公开(公告)号：EP1352395B1
公开(公告)日：2004-06-02
申请号：EP01990315.2
申请日：2001-12-18
IPC分类号： G11C29/00
摘要： A circuit arrangement for triggering a programmable connection (1), for example a fuse, is disclosed, comprising a trigger circuit (2) for triggering the fuse (1), dependent upon a signal applied to the data input (11), and a volatile memory (4), the output of which is preferably directly connected to the data input (11) of the trigger circuit. A trigger circuit for the particularly rapid and simple programming of fuses, in particular electrical programmable fuses is thus disclosed.
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公开(公告)号：EP1352395A2
公开(公告)日：2003-10-15
申请号：EP01990315.2
申请日：2001-12-18
IPC分类号： G11C29/00
摘要： A circuit arrangement for triggering a programmable connection (1), for example a fuse, is disclosed, comprising a trigger circuit (2) for triggering the fuse (1), dependent upon a signal applied to the data input (11), and a volatile memory (4), the output of which is preferably directly connected to the data input (11) of the trigger circuit. A trigger circuit for the particularly rapid and simple programming of fuses, in particular electrical programmable fuses is thus disclosed.
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公开(公告)号：EP1384233B1
公开(公告)日：2004-10-20
申请号：EP01990314.5
申请日：2001-12-18
摘要： The invention relates to a circuit arrangement for controlling a programmable connection (1), which comprises a trigger circuit (2) for selecting and burning the fuse (1), and which comprises a shift register (3), with which an activating signal (B, B') can be supplied to the trigger circuit (2). In a preferred embodiment, a volatile memory location (5) can be provided in order to provide the data that initiates the burning. The circuit arrangement enables a burning of fuses (1) and thus permits the repair of defective memory locations in bulk storage devices even after a chip having the bulk storage device has been embedded. In addition, the aforementioned shift register (3) effectively prevents the occurrence of impermissibly high currents due to the simultaneous burning of too many fuses (1).
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公开(公告)号：EP1384233A2
公开(公告)日：2004-01-28
申请号：EP01990314.5
申请日：2001-12-18
摘要： The invention relates to a circuit arrangement for controlling a programmable connection (1), which comprises a trigger circuit (2) for selecting and burning the fuse (1), and which comprises a shift register (3), with which an activating signal (B, B') can be supplied to the trigger circuit (2). In a preferred embodiment, a volatile memory location (5) can be provided in order to provide the data that initiates the burning. The circuit arrangement enables a burning of fuses (1) and thus permits the repair of defective memory locations in bulk storage devices even after a chip having the bulk storage device has been embedded. In addition, the aforementioned shift register (3) effectively prevents the occurrence of impermissibly high currents due to the simultaneous burning of too many fuses (1).
摘要翻译： 本发明涉及用于控制可编程连接（1）的电路装置，该可编程连接包括用于选择和烧断熔丝（1）的触发电路（2），并且包括移位寄存器（3），利用该移位寄存器 B，B'）可以提供给触发电路（2）。 在优选实施例中，可提供易失性存储器位置（5）以提供启动燃烧的数据。 该电路装置能够烧毁熔丝（1），因此即使在具有大容量存储装置的芯片已经被嵌入之后也能够修复大容量存储装置中的有缺陷的存储位置。 另外，上述移位寄存器（3）有效地防止了由于同时燃烧太多熔丝（1）而出现不允许的高电流。
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公开(公告)号：EP1344225A2
公开(公告)日：2003-09-17
申请号：EP01271638.7
申请日：2001-12-04
IPC分类号： G11C29/00
摘要： The invention relates to a circuit arrangement for controlling a programmable connection (1), comprising a volatile memory cell (5), which is coupled to the fuse (1) for permanently memorising the data that is stored in the volatile memory (5) and a shift register (3), which permits data to be read from the volatile memory cell (5) and data to be written to the memory cell (5). To control several fuses (1), several shift registers (3) can be interconnected to form a shift register chain. Said shift register chain (3) enables the rapid reading from and writing to the volatile memory (4), using a circuit of low complexity.
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7.发明授权
公开(公告)号：EP1097460B1
公开(公告)日：2002-06-05
申请号：EP99945908.4
申请日：1999-07-05
IPC分类号： G11C29/00
CPC分类号： G06F11/2635 , G01R31/31813
摘要： The invention relates to an integrated circuit comprising a self-test device (B) for executing a self-test of the integrated circuit which has a control output (CTR). The integrated circuit also comprises a program memory (MI) which is connected to the self-test device and which is provided for storing at least one test program (P) that is supplied from outside the integrated circuit. Said test program is ran by the self-test device during the execution of a self-test. The self-test device (B) controls the loading of the respective test program to be ran into the program memory from outside the integrated circuit via the control output (CTR) thereof.
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8.发明公开
公开(公告)号：EP1097460A2
公开(公告)日：2001-05-09
申请号：EP99945908.4
申请日：1999-07-05
IPC分类号： G11C29/00
CPC分类号： G06F11/2635 , G01R31/31813
摘要： The invention relates to an integrated circuit comprising a self-test device (B) for executing a self-test of the integrated circuit which has a control output (CTR). The integrated circuit also comprises a program memory (MI) which is connected to the self-test device and which is provided for storing at least one test program (P) that is supplied from outside the integrated circuit. Said test program is ran by the self-test device during the execution of a self-test. The self-test device (B) controls the loading of the respective test program to be ran into the program memory from outside the integrated circuit via the control output (CTR) thereof.
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