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    HARDWARE POWER-ON INITIALIZATION OF AN SOC THROUGH A DEDICATED PROCESSOR
    1.
    发明公开
    HARDWARE POWER-ON INITIALIZATION OF AN SOC THROUGH A DEDICATED PROCESSOR 审中-公开

    公开(公告)号：EP3391205A1

    公开(公告)日：2018-10-24

    申请号：EP16806355.0

    申请日：2016-11-15

    申请人： Xilinx, Inc.

    发明人： ANSARI, Ahmad, R.

    IPC分类号： G06F9/44

    CPC分类号： G06F9/4403 ,  G06F9/4401 ,  G06F11/2284 ,  G06F11/2635 ,  G06F15/781 ,  G06F2011/2278

    摘要： In an example, a system-on-chip (SoC) includes a hardware power-on-reset (POR) sequencer circuit coupled to a POR pin. The SoC further includes a platform management unit (PMU) circuit, coupled to the hardware POR sequencer circuit, the PMU including one or more central processing units (CPUs) and a read only memory (ROM). The SoC further includes one or more processing units configured to execute a boot process. The hardware POR sequencer circuit is configured to initialize the PMU. The one or more CPUs of the PMU are configured to execute code stored in the ROM to perform a pre-boot initialization.

    AUTOMATICALLY RERUNNING TEST EXECUTIONS
    2.
    发明公开
    AUTOMATICALLY RERUNNING TEST EXECUTIONS 审中-公开
    自动重测试执行

    公开(公告)号：EP3238068A1

    公开(公告)日：2017-11-01

    申请号：EP14909209.0

    申请日：2014-12-23

    申请人： Entit Software LLC

    发明人： ELIMELEH, Hofit ,  KACHKO, Noam ,  BARUCH, Gil

    IPC分类号： G06F11/26

    CPC分类号： G06F11/3688 ,  G06F11/263 ,  G06F11/2635 ,  G06F17/18 ,  G06F17/30

    摘要： Example implementations relate to automatically rerunning test executions. Some implementations may capture data during executions of a test. The data may include test status data, test rerun data, test owner data, and/or code committer data. Some implementations may also dynamically determine, for a failed execution of the test, a number of reruns to execute based on the captured data. Additionally, some implementations may cause in response to the dynamic determination, automatic rerun executions of the test until one of the rerun executions passes, the rerun executions being performed up to the number of times.

    摘要翻译： 示例实现涉及自动重新运行测试执行。 某些实现可能会在执行测试期间捕获数据。 数据可以包括测试状态数据，测试重新运行数据，测试所有者数据和/或代码提交者数据。 一些实施方案还可以为测试失败的执行动态地确定基于捕获的数据执行的重执行次数。 另外，一些实现可以响应于动态确定而引起测试的自动重新运行执行，直到重新运行的执行之一通过，重新执行的执行被执行直到次数。

    SELF-TEST ELECTRONIC ASSEMBLY AND TEST SYSTEM
    3.
    发明公开
    SELF-TEST ELECTRONIC ASSEMBLY AND TEST SYSTEM 有权
    自我评价电子设备及其测试方法

    公开(公告)号：EP1203294A1

    公开(公告)日：2002-05-08

    申请号：EP00945344.0

    申请日：2000-07-12

    申请人： Tivo, Inc.

    发明人： BARTON, James, M. ,  TAHMASSEBI, Shahin ,  PLATT, David

    IPC分类号： G06F11/267 ,  G06F11/22 ,  G06F11/00 ,  G06F11/273

    CPC分类号： G06F11/2635 ,  G06F11/006 ,  G06F11/2236 ,  G06F11/2268 ,  G06F11/2294

    摘要： A self-test electronic assembly performs self-testing, such as diagnostic or run-in testing of components and circuits, based upon internally stored test procedures. The results of self-testing are stored internally to the device, providing valuable information regarding the self-test electronic assembly, both during the manufacturing process, and preferably for ongoing in-situ operation. A test system is preferably linked to one or more self-test electronic assemblies, and provides loopback circuitry for each installed self-test electronic assembly, whereby the self-test electronic assemblies can further test components, circuitry, and security encoding and decoding operation. The preferred test rack also provides efficient and consistent monitoring and quality control over the self-testing of self-test electronic assemblies. During in-situ operation, the self-test electronic assemblies preferably monitor operating parameters, and continue to periodically perform self-testing, while storing the information within the device, and preferably transmitting the information to an external location.

    ON-CHIP METHOD AND APPARATUS FOR TESTING SEMICONDUCTOR CIRCUITS
    6.
    发明公开
    ON-CHIP METHOD AND APPARATUS FOR TESTING SEMICONDUCTOR CIRCUITS 审中-公开
    ON-芯片测试半导体电路和方法的装置

    公开(公告)号：EP1378080A1

    公开(公告)日：2004-01-07

    申请号：EP02715144.8

    申请日：2002-03-14

    申请人： ADVANCED TECHNOLOGY MATERIALS, INC.

    发明人： BARNETT, Philip C.

    IPC分类号： H04B17/00

    CPC分类号： G06F11/2635 ,  G01R31/3187

    摘要： A semiconductor circuit is disclosed that contains test hardware (100) or test software (or both) that allows test functions to be executed directly from the memory of the semiconductor circuit. A remote testing station can issue a command indicating a specific test function that should be implemented. The disclosed semiconductor circuit independently performs the indicated test and provides the results to the test station. For an exemplary memory test, the test hardware and test software are employed to initially clear the memory and thereafter selectively apply a pattern to memory and read the applied pattern from each address to confirm that the correct pattern has been stored. The testing technique of the present invention reduces the number of pins that must be contacted by the tester, such as the address pins. In addition, the reduced number of contact points allows a number of semiconductor circuits to be setup and tested in parallel using the same automated test equipment (ATE).

    INTEGRIERTE SCHALTUNG MIT EINER SELBSTTESTEINRICHTUNG ZUR DURCHFÜHRUNG EINES SELBSTTESTS DER INTEGRIERTEN SCHALTUNG
    7.
    发明授权
    INTEGRIERTE SCHALTUNG MIT EINER SELBSTTESTEINRICHTUNG ZUR DURCHFÜHRUNG EINES SELBSTTESTS DER INTEGRIERTEN SCHALTUNG 有权
    具有自试验装置具体实施自测试的集成电路的集成电路

    公开(公告)号：EP1097460B1

    公开(公告)日：2002-06-05

    申请号：EP99945908.4

    申请日：1999-07-05

    申请人： Infineon Technologies AG

    发明人： KAISER, Robert ,  SCHAMBERGER, Florian

    IPC分类号： G11C29/00

    CPC分类号： G06F11/2635 ,  G01R31/31813

    摘要： The invention relates to an integrated circuit comprising a self-test device (B) for executing a self-test of the integrated circuit which has a control output (CTR). The integrated circuit also comprises a program memory (MI) which is connected to the self-test device and which is provided for storing at least one test program (P) that is supplied from outside the integrated circuit. Said test program is ran by the self-test device during the execution of a self-test. The self-test device (B) controls the loading of the respective test program to be ran into the program memory from outside the integrated circuit via the control output (CTR) thereof.

    INTEGRIERTE SCHALTUNG MIT EINER SELBSTTESTEINRICHTUNG ZUR DURCHFÜHRUNG EINES SELBSTTESTS DER INTEGRIERTEN SCHALTUNG
    8.
    发明公开
    INTEGRIERTE SCHALTUNG MIT EINER SELBSTTESTEINRICHTUNG ZUR DURCHFÜHRUNG EINES SELBSTTESTS DER INTEGRIERTEN SCHALTUNG 有权
    具有自试验装置具体实施自测试的集成电路的集成电路

    公开(公告)号：EP1097460A2

    公开(公告)日：2001-05-09

    申请号：EP99945908.4

    申请日：1999-07-05

    申请人： Infineon Technologies AG

    发明人： KAISER, Robert ,  SCHAMBERGER, Florian

    IPC分类号： G11C29/00

    CPC分类号： G06F11/2635 ,  G01R31/31813

    摘要： The invention relates to an integrated circuit comprising a self-test device (B) for executing a self-test of the integrated circuit which has a control output (CTR). The integrated circuit also comprises a program memory (MI) which is connected to the self-test device and which is provided for storing at least one test program (P) that is supplied from outside the integrated circuit. Said test program is ran by the self-test device during the execution of a self-test. The self-test device (B) controls the loading of the respective test program to be ran into the program memory from outside the integrated circuit via the control output (CTR) thereof.

    Logic module for implementing system changes on pc architecture computers
    9.
    发明公开
    Logic module for implementing system changes on pc architecture computers 失效
    LogikmodulfürSystemänderungeneines Computers mit PC-Architektur

    公开(公告)号：EP0871125A1

    公开(公告)日：1998-10-14

    申请号：EP98106489.2

    申请日：1998-04-08

    申请人： AITM Associates, Incorporated

    发明人： Craft, Thomas W. ,  Dobbs, Donald Lee

    IPC分类号： G06F11/20 ,  G06F1/14

    CPC分类号： G06F8/78 ,  G06F1/14 ,  G06F8/66 ,  G06F11/2284 ,  G06F11/2635

    摘要： A system, method and apparatus including a logic module, preferably embodied as an electronic card that operates in combination with a PC to correct errors caused by deficiencies existing in logic residing on the PC ' s motherboard, such as the PC ' s BIOS. The preferred logic card includes a transceiver module, a memory module (e.g. an EPROM or Masked ROM) containing storage elements and executable code stored as pages. The preferred logic card also includes a page register module (64) in communication with the transceiver (56) and the memory (54), and a paging mechanism that cooperates with the page register (64) and the transceiver (56) for allowing only a predetermined amount of bytes (pages) of executable code to be accessible for operation in the PC ' s main-memory in order to correct errors caused by deficiencies existing in logic residing on the PC ' s motherboard.

    摘要翻译： 一种包括逻辑模块的系统，方法和装置，优选地实施为与PC结合操作的电子卡，以校正由驻留在PC的主板（例如PC的BIOS）上的逻辑中存在的缺陷引起的错误。 优选的逻辑卡包括收发器模块，包含存储元件的存储器模块（例如，EPROM或掩蔽ROM），以及作为页面存储的可执行代码。 优选的逻辑卡还包括与收发器（56）和存储器（54）通信的页寄存器模块（64），以及与页寄存器（64）和收发器（56）协作以仅允许的寻呼机制 预定量的可执行代码的字节（页）可在PC的主存储器中操作，以便校正由存在于PC主板上的逻辑中存在的缺陷引起的错误。