公开(公告)号：EP1042805A1

公开(公告)日：2000-10-11

申请号：EP98965122.9

申请日：1998-12-15

申请人： Infineon Technologies AG

发明人： TEMPEL, Georg ,  KUTTER, Christoph

IPC分类号： H01L21/8247

CPC分类号： H01L27/11517

摘要： A process is disclosed for producing a memory cell array, in particular en EPROM or EEPROM memory cell array with a silicon substrate (2), insulating zones (1) arranged on the silicon substrate (2) and word-lines (3-6) arranged on the insulating zones (1). The process has the following steps: the insulating zones (1) are buried in the silicon substrate by the STI (shallow trench isolation) technique; the word lines (3-6) are formed on the insulating zones (1); the word lines (3-6) are covered with a hard mask (7a-7d) and side wall oxides (8a-8h); an oxide or nitride is laterally deposited by CVD on the hard mask (7a-7d) and side wall oxides (8a-(h) to create a spacer (9a-9h); spacer channels (10a, 10b, 10c) are etched in the insulating zones (1) between adjacent word lines (3-6); an SAS (self-aligned source) lacquer mask (11a, 11b) is applied in such a way that every two adjacent, coated word lines (3, 4; 5, 6) located on mutually opposite sections, including the space channel (10a, 10c) located between these word lines, are masked, while every two adjacent, masked word lines (4, 5) of the masked pairs of word lines (3, 4; 5, 6) remain unmasked on mutually opposite sections; the SAS lacquer mask (11a, 11b) is exposed to light; the regions of the insulating zones (1) which are not covered by the SAS perforated mask (11a, 11b) are anisotropically etched while lowering the bottom (12) of the non-covered spacer channels (10b) down to at least the surface of the exposed silicon substrate (2); and the SAS perforated mask (11a, 11b) is removed to expose the resultant structure.

公开(公告)号：EP1240670A1

公开(公告)日：2002-09-18

申请号：EP99968315.4

申请日：1999-12-20

申请人： Infineon Technologies AG

发明人： STEIN VON KAMIENSKI, Elard ,  WAWER, Peter ,  LUDWIG, Christoph ,  KUTTER, Christoph ,  GEORGAKOS, Georg ,  LIEBELT, Andreas ,  KRIZ, Jakob ,  HUCKELS, Kai

IPC分类号： H01L27/115

CPC分类号： H01L27/11519 ,  G11C16/0416 ,  H01L27/11521

摘要： The invention relates to a non-volatile NOR semiconductor memory device and method for the programming thereof, whereby a number of single transistor memory cells (SZ), arranged in the form of a matrix, may be controlled by either word lines (WL) or by bit lines (BL). Each single transistor memory cell (SZ), thus possesses both a source line (S1, S2) and a drain line (D1, D2), by means of which a selective control of the respective source and drain regions (D, S) is achieved. The leak current can thus be optimally reduced in the semiconductor memory device with minimal space requirement.

公开(公告)号：EP1042805B1

公开(公告)日：2004-11-10

申请号：EP98965122.9

申请日：1998-12-15

申请人： Infineon Technologies AG

发明人： TEMPEL, Georg ,  KUTTER, Christoph

IPC分类号： H01L21/8247

CPC分类号： H01L27/11517

摘要： A process is disclosed for producing a memory cell array, in particular en EPROM or EEPROM memory cell array with a silicon substrate (2), insulating zones (1) arranged on the silicon substrate (2) and word-lines (3-6) arranged on the insulating zones (1). The process has the following steps: the insulating zones (1) are buried in the silicon substrate by the STI (shallow trench isolation) technique; the word lines (3-6) are formed on the insulating zones (1); the word lines (3-6) are covered with a hard mask (7a-7d) and side wall oxides (8a-8h); an oxide or nitride is laterally deposited by CVD on the hard mask (7a-7d) and side wall oxides (8a-(h) to create a spacer (9a-9h); spacer channels (10a, 10b, 10c) are etched in the insulating zones (1) between adjacent word lines (3-6); an SAS (self-aligned source) lacquer mask (11a, 11b) is applied in such a way that every two adjacent, coated word lines (3, 4; 5, 6) located on mutually opposite sections, including the space channel (10a, 10c) located between these word lines, are masked, while every two adjacent, masked word lines (4, 5) of the masked pairs of word lines (3, 4; 5, 6) remain unmasked on mutually opposite sections; the SAS lacquer mask (11a, 11b) is exposed to light; the regions of the insulating zones (1) which are not covered by the SAS perforated mask (11a, 11b) are anisotropically etched while lowering the bottom (12) of the non-covered spacer channels (10b) down to at least the surface of the exposed silicon substrate (2); and the SAS perforated mask (11a, 11b) is removed to expose the resultant structure.

公开(公告)号：EP1192652A1

公开(公告)日：2002-04-03

申请号：EP00943661.9

申请日：2000-05-30

申请人： Infineon Technologies AG

发明人： WAWER, Peter ,  SPRINGMANN, Oliver ,  WOLF, Konrad ,  HEITZSCH, Olaf ,  HUCKELS, Kai ,  RENNEKAMP, Reinhold ,  RÖHRICH, Mayk ,  STEIN VON KAMIENSKI, Elard ,  KUTTER, Christoph ,  LUDWIG, Christoph

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/7883

摘要： The invention relates to method of producing a non-volatile semiconductor memory cell (SZ) with a separate tunnel window cell (TF). A tunnel section (TG) is formed in a late implantation step by tunnel implantation (IT) using the tunnel window cell (TF) as a matrix. The inventive method provides a memory cell that requires a minimum of space and allows for a high quantity of program/erase cycles.