公开(公告)号：EP1573819B1

公开(公告)日：2011-04-20

申请号：EP03782114.7

申请日：2003-11-27

申请人： Infineon Technologies AG

发明人： BACHMANN, Jens ,  FÖSTE, Bernd ,  GOLLER, Klaus ,  KRIZ, Jakob

IPC分类号： H01L27/08

CPC分类号： H01L27/0805

摘要： The invention relates to, among other things, a method for producing a capacitor assembly (110) containing at least three electrodes (114a, 118a and 122b). The capacitor assembly (110) is produced using a number of lithographic processes that is less than the number of electrodes (114a, 118a and 122b). The invention also relates to a capacitor assembly that extends over more than two or more than three intermediate layers between metallization layers. The circuit arrangement has a high capacitance density and can be produced in a simple manner. The invention additionally relates to a method during which an electrode layer is firstly structured by means of a dry etching process. Remnants of the electrode layer are removed by means of a wet-chemical process. These measures enable the production of capacitors with excellent electrical properties.

公开(公告)号：EP1307920A2

公开(公告)日：2003-05-07

申请号：EP01962611.8

申请日：2001-08-06

申请人： Infineon Technologies AG

发明人： PALM, Herbert ,  WILLER, Josef ,  GRATZ, Achim ,  KRIZ, Jakob ,  RÖHRICH, Mayk

IPC分类号： H01L27/115 ,  H01L21/8246 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

摘要： Each memory cell is a memory transistor which is provided with a gate electrode (2) on the upper surface of a semiconductor body. Said gate electrode is disposed in a trench between a source area (3) and a drain area (4) which are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by dielectric material. A series of oxide nitride-oxide layers (5, 6, 7) is disposed between the source area and the drain area and between the drain area and the gate electrode in order to capture charge carriers on the source and drain.

公开(公告)号：EP4184585A1

公开(公告)日：2023-05-24

申请号：EP21210079.6

申请日：2021-11-23

申请人： Infineon Technologies AG

发明人： FUCHS, Cornelius ,  KRIZ, Jakob ,  MARKERT, Matthias

IPC分类号： H01L27/32 ,  H05B33/06

摘要： Substrate arrangement for a micro display, the substrate arrangement comprising a semiconductor substrate, a back end of line (BEOL) stack, wherein the BEOL stack is arranged on the semiconductor substrate and wherein the BEOL stack comprises a plurality of structured wiring layers, an insulating material structure (IMS), and a recess in the IMS, wherein the plurality of structured wiring layers are stacked and embedded in the insulating material structure, and wherein an upmost structured wiring layer of the plurality of structured wiring layers comprises a plurality of contact pads, and wherein the recess extends to a first set of contact pads of the plurality of contact pads; and a conductive layer, having a metallic material, on the surface of the BEOL stack, wherein the conductive layer comprises a first, structured portion comprising a contact pad array and wherein the conductive layer comprises a second portion that is arranged on the first set of contact pads of the BEOL stack , and wherein the first portion of the conductive layer is electrically separated from the second portion of the conductive layer; and wherein the first set of contact pads of the BEOL stack and the second portion of the conductive layer are configured to form recessed wire-bond pads.

公开(公告)号：EP1573819A1

公开(公告)日：2005-09-14

申请号：EP03782114.7

申请日：2003-11-27

申请人： Infineon Technologies AG

发明人： BACHMANN, Jens ,  FÖSTE, Bernd ,  GOLLER, Klaus ,  KRIZ, Jakob

IPC分类号： H01L27/08

CPC分类号： H01L27/0805

摘要： The invention relates to, among other things, a method for producing a capacitor assembly (110) containing at least three electrodes (114a, 118a and 122b). The capacitor assembly (110) is produced using a number of lithographic processes that is less than the number of electrodes (114a, 118a and 122b). The invention also relates to a capacitor assembly that extends over more than two or more than three intermediate layers between metallization layers. The circuit arrangement has a high capacitance density and can be produced in a simple manner. The invention additionally relates to a method during which an electrode layer is firstly structured by means of a dry etching process. Remnants of the electrode layer are removed by means of a wet-chemical process. These measures enable the production of capacitors with excellent electrical properties.

公开(公告)号：EP1702369A1

公开(公告)日：2006-09-20

申请号：EP04802810.4

申请日：2004-11-24

申请人： Infineon Technologies AG

发明人： SEZI, Recai ,  WALTER, Andreas ,  ENGL, Reimund ,  MALTENBERGER, Anna ,  DEHM, Christine ,  SITARAM, Arkalgud ,  KASKO, Ihar ,  NÜTZEL, Joachim ,  KRIZ, Jakob ,  MIKOLAJICK, Thomas ,  PINNOW, Cay-Uwe

IPC分类号： H01L51/00 ,  H01L51/05

CPC分类号： H01L51/0036 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L27/28 ,  H01L51/0051 ,  H01L51/0062 ,  H01L51/0595

摘要： The invention relates to a semiconductor arrangement comprising at least one non-volatile memory cell that is provided with a first electrode which consists of at least two layers. Said semiconductor arrangement further comprises an organic material that forms a bond with the layer of the first electrode, which is in direct contact therewith. The invention also relates to a method for producing said non-volatile memory cell, a semiconductor arrangement comprising a plurality of inventive memory cells, and a method for the production thereof.

公开(公告)号：EP1407484A2

公开(公告)日：2004-04-14

申请号：EP02753085.6

申请日：2002-07-10

申请人： Infineon Technologies AG

发明人： KRIZ, Jakob ,  SECK, Martin ,  TILKE, Armin

IPC分类号： H01L21/331 ,  H01L29/737

CPC分类号： H01L29/66272 ,  H01L21/2257

摘要： The invention relates to a method for producing a bipolar transistor comprising a polysilicon emitter, according to which a collector region (12) of a first conductivity type and an adjacent base region (14) of a second conductivity type are created. At least one layer (16) consisting of an insulating material is then applied, said layer or layers being structured in such a way that at least one section of the base region (14) is exposed. A layer consisting of a polycrystalline semiconductor material of the first conductivity type, which is highly doped with doping atoms, is subsequently created, in such a way that the exposed section is essentially covered. A second layer (20) consisting of a highly conductive material is then created on the layer (18) consisting of the polycrystalline semiconductor material, forming a dual-layer emitter with the latter. At least one portion of the doping atoms of the first conductivity type of the highly doped polycrystalline semiconductor layer is then caused to diffuse into the base region (14), to create an emitter region (22) of the first conductivity type.

公开(公告)号：EP1240670A1

公开(公告)日：2002-09-18

申请号：EP99968315.4

申请日：1999-12-20

申请人： Infineon Technologies AG

发明人： STEIN VON KAMIENSKI, Elard ,  WAWER, Peter ,  LUDWIG, Christoph ,  KUTTER, Christoph ,  GEORGAKOS, Georg ,  LIEBELT, Andreas ,  KRIZ, Jakob ,  HUCKELS, Kai

IPC分类号： H01L27/115

CPC分类号： H01L27/11519 ,  G11C16/0416 ,  H01L27/11521

摘要： The invention relates to a non-volatile NOR semiconductor memory device and method for the programming thereof, whereby a number of single transistor memory cells (SZ), arranged in the form of a matrix, may be controlled by either word lines (WL) or by bit lines (BL). Each single transistor memory cell (SZ), thus possesses both a source line (S1, S2) and a drain line (D1, D2), by means of which a selective control of the respective source and drain regions (D, S) is achieved. The leak current can thus be optimally reduced in the semiconductor memory device with minimal space requirement.