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    BITLINE CONTACTS IN A MEMORY CELL ARRAY
    1.
    发明公开
    BITLINE CONTACTS IN A MEMORY CELL ARRAY 审中-公开
    在一个存储单元矩阵位线

    公开(公告)号：EP1390981A2

    公开(公告)日：2004-02-25

    申请号：EP02735387.9

    申请日：2002-05-27

    申请人： Infineon Technologies AG

    发明人： SCHWALBE, Grit ,  WANG, Kae-Horng ,  FELDNER, Klaus ,  STEIN VON KAMIENSKI, Elard

    IPC分类号： H01L27/105 ,  H01L21/8239 ,  H01L27/112 ,  H01L21/8246 ,  H01L21/768

    CPC分类号： H01L27/11568 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/112

    摘要： The present invention provides a method for providing bitline contacts in a memory cell array which comprises a plurality of bitlines (2) arranged in a first direction, said bitlines (2) being covered by an isolating layer (3), a plurality of wordlines (4) arranged in a second direction perpendicular to said first direction above said bitlines, memory cells being disposed at the points at which said bitlines (2) and word-lines (4) cross each other. According to a first aspect of the present invention, the isolating layer (3) is removed from the bitlines (2) at the portions which are not covered by the wordlines (4), whereas the areas between the bitlines (2) remain unaffected. Alternatively, the isolating layer (3) is removed from the whole cell array. Then, an electrical conductive material (18) is provided on the exposed portions of said bitlines (2).The method is used to provide bitline contacts in a nitride read only memory (NROMTM) chip.

    TRENCH FORMATION AND OXIDE ETCHING PROCESS
    4.
    发明公开
    TRENCH FORMATION AND OXIDE ETCHING PROCESS 有权
    GRABEN-HERSTELLUNGSVERFAHREN UND OXID-ÄTVERVERHHEN

    公开(公告)号：EP1312113A1

    公开(公告)日：2003-05-21

    申请号：EP01971855.0

    申请日：2001-08-02

    申请人： Infineon Technologies AG

    发明人： ABDUL-HAK, Ayad ,  LUDWIG, Christoph ,  STEIN VON KAMIENSKI, Elard ,  GRATZ, Achim ,  RENNEKAMP, Reinhold ,  WAWER, Peter

    IPC分类号： H01L21/762 ,  H01L21/311 ,  H01L21/32 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/336

    CPC分类号： H01L21/76232 ,  H01L21/823481

    摘要： A process for producing a semiconductor configuration includes the steps of providing a semiconductor substrate, providing a buffer oxide layer (40) on the semiconductor substrate and providing a hard mask on the buffer oxide layer. An STI trench is etched by using the hard mask and a liner oxide layer (20) is provided in the STI trench. The hard mask is removed to expose the buffer oxide layer and the buffer oxide layer is removed by an etching process. The buffer oxide layer is etched more rapidly than the liner oxide layer in the etching process. A gate oxide layer is provided on the semiconductor substrate. A semiconductor configuration is also provided.

    摘要翻译： 一种制造半导体结构的方法包括以下步骤：提供半导体衬底，在半导体衬底上提供缓冲氧化物层，并在缓冲氧化物层上提供硬掩模。 通过使用硬掩模蚀刻STI沟槽，并且在STI沟槽中提供衬垫氧化物层。 去除硬掩模以暴露缓冲氧化物层，并通过蚀刻工艺除去缓冲氧化物层。 在蚀刻过程中，缓冲氧化物层比衬垫氧化物层蚀刻得更快。 在半导体衬底上设置栅氧化层。 还提供半导体配置。