公开(公告)号：EP2115562B1

公开(公告)日：2013-01-23

申请号：EP07865319.3

申请日：2007-12-06

申请人： Intel Corporation

发明人： GOPAL, Vindoh ,  WOLRICH, Gilbert ,  YAP, Kirk ,  FEGHALI, Wajdi ,  VRANICH, John ,  OTTAVI, Robert

IPC分类号： G06F11/10 ,  G06F7/72

CPC分类号： G06F11/1076 ,  G06F2211/1057

公开(公告)号：EP2115562A1

公开(公告)日：2009-11-11

申请号：EP07865319.3

申请日：2007-12-06

申请人： Intel Corporation

发明人： GOPAL, Vindoh ,  WOLRICH, Gilbert ,  YAP, Kirk ,  FEGHALI, Wajdi ,  VRANICH, John ,  OTTAVI, Robert

IPC分类号： G06F3/06

CPC分类号： G06F11/1076 ,  G06F2211/1057

摘要： An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.

公开(公告)号：EP3031167B1

公开(公告)日：2019-02-06

申请号：EP14834842.8

申请日：2014-08-08

申请人： Intel Corporation

发明人： GOPAL, Vindoh ,  FEGHALI, Wajdi K.

IPC分类号： H04L9/06 ,  G06F9/30

公开(公告)号：EP1984846A2

公开(公告)日：2008-10-29

申请号：EP07751177.2

申请日：2007-02-14

申请人： Intel Corporation ,  Cutter, Daniel

发明人： CUTTER, Daniel ,  FEGHALI, Wajdi ,  HASENPLAUGH, William ,  WOLRICH, Gilbert ,  GOPAL, Vindoh

IPC分类号： G06F15/76

CPC分类号： G06F9/30145 ,  G06F7/5324 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/383 ,  G06F21/602 ,  G06F21/72

摘要： In general, in one aspect, the disclosure describes a processing unit that includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control store of program instructions, the control logic to process instructions including an instruction to transfer data from the input buffer to the memory and an instruction to cause the arithmetic logic unit to perform an operation on operands provided by at least one of the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.

公开(公告)号：EP3031167A1

公开(公告)日：2016-06-15

申请号：EP14834842.8

申请日：2014-08-08

申请人： Intel Corporation

发明人： GOPAL, Vindoh ,  FEGHALI, Wajdi K.

IPC分类号： H04L9/06 ,  G06F9/30

CPC分类号： H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  H04L9/0625

摘要： Instructions and logic provide secure cipher hashing algorithm round functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a secure cipher hashing algorithm, the first instruction specifying a source data, and one or more key operands. Processor execution units, are responsive to the decoded instruction, to perform one or more secure cipher hashing algorithm round iterations upon the source data, using the one or more key operands, and store a result of the instruction in a destination register. One embodiment of the instruction specifies a secure cipher hashing algorithm round iteration using a Feistel cipher algorithm such as DES or TDES. In one embodiment a result of the instruction may be used in generating a resource assignment from a request for load balancing requests across the set of processing resources.

公开(公告)号：EP2033357A2

公开(公告)日：2009-03-11

申请号：EP07812243.9

申请日：2007-06-21

申请人： Intel Corporation

发明人： HASENPLAUGH, William ,  GOPAL, Vindoh ,  GAUBATZ, Gunnar

IPC分类号： H04L9/06 ,  H04L9/28 ,  G06F9/06 ,  G06F15/16

CPC分类号： G06F7/72

摘要： Techniques are described to determine N mod M, where N is a number having a width of n-bits, and M is a number having a width of m-bits. The techniques, generally, involve determining N' = NH 2f mod M + NL and, subsequently, determining N' mod M.