公开(公告)号：EP1984846A2

公开(公告)日：2008-10-29

申请号：EP07751177.2

申请日：2007-02-14

申请人： Intel Corporation ,  Cutter, Daniel

发明人： CUTTER, Daniel ,  FEGHALI, Wajdi ,  HASENPLAUGH, William ,  WOLRICH, Gilbert ,  GOPAL, Vindoh

IPC分类号： G06F15/76

CPC分类号： G06F9/30145 ,  G06F7/5324 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/383 ,  G06F21/602 ,  G06F21/72

摘要： In general, in one aspect, the disclosure describes a processing unit that includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control store of program instructions, the control logic to process instructions including an instruction to transfer data from the input buffer to the memory and an instruction to cause the arithmetic logic unit to perform an operation on operands provided by at least one of the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.

公开(公告)号：EP1493081B1

公开(公告)日：2010-11-03

申请号：EP03734963.6

申请日：2003-01-16

申请人： Intel Corporation

发明人： ADILETTA, Matthew ,  BERNSTEIN, Debra ,  ROSENBLUTH, Mark ,  WOLRICH, Gilbert

IPC分类号： G06F9/38 ,  G06F13/16

CPC分类号： G06F9/3824 ,  G06F9/3851

摘要： A method for transferring data between programming agents and memory resources. The method includes transferring data between a processing agent and a memory resource, designating the memory resource for pushing the data to the processing agent via a push bus having a plurality of sources that arbitrate use of the push bus, and designating the memory resource for receiving the data from the processing agent via a pull bus having a plurality of destinations that arbitrate use of the pull bus.

公开(公告)号：EP1282862B1

公开(公告)日：2010-04-14

申请号：EP00993654.3

申请日：2000-12-06

申请人： Intel Corporation

发明人： WOLRICH, Gilbert ,  BERNSTEIN, Debra ,  ADILETTA, Matthew, J. ,  WHEELER, William

IPC分类号： G06F13/00

CPC分类号： G06F13/1642

公开(公告)号：EP1242883B1

公开(公告)日：2006-09-13

申请号：EP00992412.7

申请日：2000-12-08

申请人： INTEL CORPORATION

发明人： WOLRICH, Gilbert ,  HOOPER, Donald ,  BERNSTEIN, Debra ,  ADILETTA, Matthew, J. ,  WHEELER, William

IPC分类号： G06F9/54 ,  G06F9/50

CPC分类号： G06F9/4843 ,  G06F9/3851

摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.

公开(公告)号：EP1214660B1

公开(公告)日：2004-05-19

申请号：EP00954126.9

申请日：2000-08-17

申请人： Intel Corporation

发明人： ADILETTA, Matthew, J. ,  WHEELER, William ,  REDFIELD, James ,  CUTTER, Daniel ,  WOLRICH, Gilbert

IPC分类号： G06F13/16 ,  G06F9/46

CPC分类号： G06F13/1642

摘要： A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

公开(公告)号：EP1236088A1

公开(公告)日：2002-09-04

申请号：EP00959711.3

申请日：2000-08-31

申请人： INTEL CORPORATION

发明人： WOLRICH, Gilbert ,  ADILETTA, Matthew, J. ,  WHEELER, William ,  BERNSTEIN, Debra ,  HOOPER, Donald

IPC分类号： G06F9/00 ,  G06F12/00

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/30058 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851

摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD_3 ... THREAD_0). The processor maintains execution threads (THREAD_3 ... THREAD_0). The execution threads (THREAD_3 ... THREAD_0) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD_3 ... THREAD_0).

公开(公告)号：EP1221105A2

公开(公告)日：2002-07-10

申请号：EP00954073.3

申请日：2000-08-15

申请人： Intel Corporation

发明人： ADILETTA, Matthew, J. ,  WOLRICH, Gilbert ,  WHEELER, William

IPC分类号： G06F15/78

CPC分类号： G06F9/30076 ,  G06F9/3004 ,  G06F9/3012 ,  G06F9/30127 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F15/8015

摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write reference.

公开(公告)号：EP1221086A1

公开(公告)日：2002-07-10

申请号：EP00959265.0

申请日：2000-08-17

申请人： Intel Corporation

发明人： BERNSTEIN, Debra ,  HOOPER, Donald, F. ,  ADILETTA, Matthew, J. ,  WOLRICH, Gilbert ,  WHEELER, William

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3012 ,  G06F9/30076 ,  G06F9/30127 ,  G06F9/3851

摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

公开(公告)号：EP1245097B1

公开(公告)日：2013-07-03

申请号：EP00984108.1

申请日：2000-12-07

申请人： Intel Corporation

发明人： WOLRICH, Gilbert ,  BERNSTEIN, Debra ,  ADILETTA, Matthew, J. ,  HOOPER, Donald, F.

IPC分类号： H04L12/953

CPC分类号： H04L49/351 ,  H04L49/102 ,  H04L49/352

公开(公告)号：EP2181386A2

公开(公告)日：2010-05-05

申请号：EP08772266.6

申请日：2008-06-30

申请人： Intel Corporation

发明人： GUERON, Shay ,  GOPAL, Vinodh ,  FEGHALI, Wajdi, K. ,  WOLRICH, Gilbert

IPC分类号： G06F7/52

CPC分类号： H03M13/091

摘要： A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory.