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    SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING ENDCAP PLUGS
    2.
    发明公开
    SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING ENDCAP PLUGS 审中-公开

    公开(公告)号：EP3550602A1

    公开(公告)日：2019-10-09

    申请号：EP19160416.4

    申请日：2019-03-01

    Applicant: INTEL Corporation

    Inventor： SUBRAMANIAN, Sairam ,  KENYON, Christopher ,  GOVINDARAJU, Sridhar ,  JAN, Chia-Hong ,  LIU, Mark ,  LIAO, Szuya S. ,  HAFEZ, Walid M.

    IPC: H01L21/8234 ,  H01L27/088

    Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure (832) is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure (834) is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.

    GATE ISOLATION IN NON-PLANAR TRANSISTORS
    5.
    发明公开
    GATE ISOLATION IN NON-PLANAR TRANSISTORS 审中-公开

    公开(公告)号：EP3394897A1

    公开(公告)日：2018-10-31

    申请号：EP15911519.5

    申请日：2015-12-26

    Applicant: Intel Corporation

    Inventor： GULER, Leonard P. ,  BHIMARASETTI, Gopinath ,  SHARMA, Vyom ,  HAFEZ, Walid M. ,  AUTH, Christopher P.

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L27/0886 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

    Abstract: An embodiment includes an apparatus comprising: first and second semiconductor fins that are parallel to each other; a first gate, on the first fin, including a first gate portion between the first and second fins; a second gate, on the second fin, including a second gate portion between the first and second fins; a first oxide layer extending along a first face of the first gate portion, a second oxide layer extending along a second face of the second gate portion, and a third oxide layer connecting the first and second oxide layers to each other; and an insulation material between the first and second gate portions; wherein the first, second, and third oxide layers each include an oxide material and the insulation material does not include the oxide material. Other embodiments are described herein.

    MULTI-GATE TRANSISTOR WITH VARIABLY SIZED FIN
    7.
    发明公开
    MULTI-GATE TRANSISTOR WITH VARIABLY SIZED FIN 审中-公开
    多门式晶体管麻醉机变压器RIPEM

    公开(公告)号：EP3161872A1

    公开(公告)日：2017-05-03

    申请号：EP14896232.7

    申请日：2014-06-27

    Applicant: Intel Corporation

    Inventor： NIDHI, Nidhi ,  JAN, Chia-Hong ,  OLAC-VAW, Roman W. ,  CHANG, Hsu-Yu ,  DIAS, Neville L. ,  HAFEZ, Walid M. ,  RAMASWAMY, Rahul

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L21/823412 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42368 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

    Abstract: An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, a drain region having a drain width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the apparatus includes at least one of (a) the channel region width being wider than the source region width, and (b) the gate dielectric including a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location, the first and second locations located at an equivalent height on the sidewall and the first and second gate dielectrics thicknesses being unequal to one another. Other embodiments are described herein.

    Abstract translation: 一个实施例包括一种装置，包括：非平面晶体管，包括鳍片，所述鳍片包括源极区域宽度和源极区域高度的源极区域，具有沟道区域宽度和沟道区域高度的沟道区域，漏极区域 具有漏极宽度和漏极高度，以及形成在沟道区域的侧壁上的栅极电介质; 其中所述装置包括以下中的至少一个：（a）所述沟道区宽度宽于所述源极区宽度，以及（b）所述栅极电介质包括在第一位置处的第一栅极电介质厚度和在第二位置处的第二栅极电介质厚度 位于侧壁上的等效高度的第一和第二位置以及第一和第二栅极电介质厚度彼此不相等。 本文描述了其它实施例。

    FIN-BASED SEMICONDUCTOR DEVICES AND METHODS
    9.
    发明公开
    FIN-BASED SEMICONDUCTOR DEVICES AND METHODS 审中-公开
    芬兰基督教圣母玛利亚

    公开(公告)号：EP3097580A1

    公开(公告)日：2016-11-30

    申请号：EP14879976.0

    申请日：2014-01-24

    Applicant: Intel Corporation

    Inventor： HAFEZ, Walid M. ,  JAN, Chia-Hong

    IPC: H01L21/336

    CPC classification number: H01L29/74 ,  H01L21/2255 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/41716 ,  H01L29/66363 ,  H01L29/785

    Abstract: Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.

    Abstract translation: 公开了半导体器件，集成电路器件和方法的实施例。 在一些实施例中，半导体器件可以包括设置在衬底上的第一鳍片和第二鳍片。 第一翅片可以具有包括设置在第二材料和基底之间的第一材料的部分，第二材料设置在第三材料和第一材料之间，第三材料设置在第四材料和第二材料之间。 第一和第三材料可以由第一类型的非本征半导体形成，并且第二和第四材料可以由第二种不同类型的非本征半导体形成。 第二翅片可以与第一翅片横向分离并且与第一，第二，第三或第四材料中的至少一个物质连接。 可以公开和/或要求保护其他实施例。

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