公开(公告)号：EP3311400A1

公开(公告)日：2018-04-25

申请号：EP15895835.5

申请日：2015-06-19

Applicant: Intel Corporation

Inventor： YANG, Xiaodong ,  LIN, Jui-Yen ,  PHOA, Kinyip ,  NIDHI, Nidhi ,  CHEN, Yi Wei ,  SHIH, Kun-huan ,  HAFEZ, Walid M. ,  TSAI, Curtis

IPC: H01L21/60

CPC classification number: H01L29/7813 ,  H01L23/481 ,  H01L29/0653 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/945

Abstract: A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.

公开(公告)号：EP4020556A1

公开(公告)日：2022-06-29

申请号：EP21196282.4

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： GUHA, Biswajeet ,  GREENE, Brian ,  SCHULMAN, Daniel ,  HSU, William ,  LIN, Chung-Hsun ,  TSAI, Curtis ,  FISCHER, Kevin

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/861

Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.

公开(公告)号：EP3050106B1

公开(公告)日：2020-11-18

申请号：EP13894350.1

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： PARK, Joodong ,  BHIMARASETTI, Gopinath ,  RAMASWAMY, Rahul ,  JAN, Chia-Hong ,  HAFEZ, Walid M. ,  YEH, Jeng-Ya D. ,  TSAI, Curtis

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/66 ,  H01L29/78

公开(公告)号：EP3050106A1

公开(公告)日：2016-08-03

申请号：EP13894350.1

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： PARK, Joodong ,  BHIMARASETTI, Gopinath ,  RAMASWAMY, Rahul ,  JAN, Chia-Hong ,  HAFEZ, Walid M. ,  YEH, Jeng-Ya D. ,  TSAI, Curtis

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10826 ,  H01L27/10808 ,  H01L27/10879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854

Abstract: Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.

Abstract translation: 描述了用于嵌入式动态随机存取存储器（eDRAM）的低泄漏非平面存取晶体管和用于制造用于eDRAM的低泄漏非平面存取晶体管的方法。 例如，半导体器件包括设置在衬底上方并且包括设置在两个宽鳍片区域之间的窄鳍区域的半导体鳍片。 栅极电极堆叠与半导体鳍片的窄鳍区域共形设置，栅电极堆叠包括设置在栅极介电层上的栅电极。 栅介质层包括下层和上层，下层由半导体鳍片的氧化物构成。 包括一对源极/漏极区域，每个源极/漏极区域设置在相应的一个宽鳍片区域中。

公开(公告)号：EP4283676A2

公开(公告)日：2023-11-29

申请号：EP23193624.6

申请日：2013-06-18

Applicant: INTEL Corporation

Inventor： YEH, Jeng-Ya D. ,  VANDERVOORN, Peter J. ,  HAFEZ, Wald M. ,  JAN, Chia-Hong ,  TSAI, Curtis ,  PARK, Joodong

IPC: H01L27/06 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

Abstract: Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

公开(公告)号：EP4044249A1

公开(公告)日：2022-08-17

申请号：EP22165476.7

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： PARK, Joodong ,  BHIMARASETTI, Gopinath ,  RAMASWAMY, Rahul ,  JAN, Chia-Hong ,  HAFEZ, Walid M. ,  YEH, Jeng-Ya D. ,  TSAI, Curtis

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/108

Abstract: Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.

公开(公告)号：EP2898533A1

公开(公告)日：2015-07-29

申请号：EP13839477.0

申请日：2013-06-18

Applicant: Intel Corporation

Inventor： YEH, Jeng-Ya, D. ,  VANDERVOORN, Peter, J. ,  HAFEZ, Walid, M. ,  JAN, Chia-Hong ,  TSAI, Curtis ,  PARK, Joodong

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823431 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/66795

Abstract: Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

公开(公告)号：EP4283676A3

公开(公告)日：2024-07-17

申请号：EP23193624.6

申请日：2013-06-18

Applicant: INTEL Corporation

Inventor： YEH, Jeng-Ya D. ,  VANDERVOORN, Peter J. ,  HAFEZ, Wald M. ,  JAN, Chia-Hong ,  TSAI, Curtis ,  PARK, Joodong

IPC: H01L27/06 ,  H10N97/00 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/66545 ,  H01L27/0886 ,  H01L21/823431

Abstract: Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

公开(公告)号：EP4202991A1

公开(公告)日：2023-06-28

申请号：EP22208176.2

申请日：2022-11-17

Applicant: Intel Corporation

Inventor： FISCHER, Kevin ,  KOBRINSKY, Mauro J. ,  TSAI, Curtis ,  NABORS, Marni ,  PULS, Conor P.

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L23/485

Abstract: Integrated circuit structures having backside power delivery are described. In an example, an integrated circuit structure includes a device layer within a cell boundary, the device layer having a front side and a backside, and the device layer including a source or drain structure. A source or drain trench contact structure is on the front side of the device layer. The source or drain trench contact structure is coupled to the source or drain structure. A metal layer is on the backside of the device layer. A via structure couples the metal layer to the source or drain trench contact structure. The via structure is overlapping and parallel with a cell row boundary of the cell boundary.

公开(公告)号：EP3767672A1

公开(公告)日：2021-01-20

申请号：EP20194428.7

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： PARK, Joodong ,  BHIMARASETTI, Gopinath ,  RAMASWAMY, Rahul ,  JAN, Chia-Hong ,  HAFEZ, Walid M. ,  YEH, Jeng-Ya D. ,  TSAI, Curtis

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/66 ,  H01L29/78

Abstract: Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.