公开(公告)号：EP4006723A2

公开(公告)日：2022-06-01

申请号：EP22152342.6

申请日：2018-03-01

Applicant: Intel Corporation

Inventor： MA, Liwel ,  SATISH, Nadathur Rajagopalan ,  BOTTLESON, Jeremy ,  AKHBARI, Farshad ,  NURVITADHI, Eriko ,  APPU, Abhishek R. ,  KOKER, Altug ,  SINHA, Kamal ,  RAY, Joydeep ,  VEMBU, Balaji ,  RANGANATHAN, Vasanth ,  JAHAGIRDAR, Sanjeev

IPC: G06F9/448 ,  G06T1/20

Abstract: A mechanism is described for facilitating fast data operations for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting input data to be used in computational tasks by a computation component of a compute pipeline of a processor including a graphics processor. The method may further include determining one or more frequently-used data values (FDVs) from the data, and pushing the one or more frequent data values to bypass the computational tasks.

公开(公告)号：EP3792839A1

公开(公告)日：2021-03-17

申请号：EP20205015.9

申请日：2018-03-02

Applicant: INTEL Corporation

Inventor： APPU, Abhishek R. ,  KOKER, Altug ,  HURD, Linda L. ,  KIM, Dukhwan ,  MACPHERSON, Mike B. ,  WEAST, John C. ,  CHEN, Feng ,  AKHBARI, Farshad ,  SRINIVASA, Narayan ,  SATISH, Nadathur Rajagopalan ,  TANG, Ping T. ,  RAY, Joydeep ,  STRICKLAND, Michael S. ,  CHEN, Xiaoming ,  YAO, Anbang ,  SHPEISMAN, Tatiana

IPC: G06N3/063 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06T1/20

Abstract: The present disclosure provides an apparatus comprising an interconnect fabric comprising one or more switches, a memory interface coupled to the interconnect fabric, an input/output (10) interface coupled to the interconnect fabric an array of processing clusters coupled to the interconnect fabric, the array of processing clusters to process instructions at variable precisions. At least one processing cluster comprising a plurality of registers to store source operands at variable precisions and an execution unit comprising a plurality of arithmetic logic units (ALUs) to execute one or more of the instructions to perform a mixed-precision fused multiply-accumulate (FMAC) operation of D = A ∗ B + C. Each source operand A, B, and C may be any of FP64, FP32, FP16, INT32, INT16, INT8 or INT4. An ALU is to generate the result operand D by multiplying source operand A with source operand B to generate an intermediate product, and adding the intermediate product to source operand C.

公开(公告)号：EP3396528A1

公开(公告)日：2018-10-31

申请号：EP18162625.0

申请日：2018-03-19

Applicant: INTEL Corporation

Inventor： KOKER, Altug ,  APPU, Abhishek R. ,  SINHA, Kamal ,  RAY, Joydeep ,  VEMBU, Balaji ,  OULD-AHMED-VALL, Elmoustapha ,  BAGHSORKHI, Sara S. ,  YAO, Anbang ,  NEALIS, Kevin ,  CHEN, Xiaoming ,  WEAST, John C. ,  GOTTSCHLICH, Justin E. ,  SURTI, Prasoonkumar ,  SAKTHIVEL, Chandrasekaran ,  AKHBARI, Farshad ,  SATISH, Nadathur Rajagopalan ,  MA, Liwei ,  BOTTLESON, Jeremy ,  NURVITADHI, Eriko ,  SCHLUESSLER, Travis T. ,  SHAH, Ankur N. ,  KENNEDY, Jonathan ,  RANGANATHAN, Vasanth ,  JAHAGIRDAR, Sanjeev

IPC: G06F9/28 ,  G06N3/04 ,  G06N3/063 ,  G06F9/50

CPC classification number: G06N3/08 ,  G06F9/505 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/0481 ,  G06N3/063 ,  G06N99/005

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：EP4369252A2

公开(公告)日：2024-05-15

申请号：EP24166744.3

申请日：2018-03-19

Applicant: INTEL Corporation

Inventor： SINHA, Kamal ,  VEMBU, Balaji ,  NURVITADHI, Eriko ,  GALOPPO VON BORRIES, Nicolas C. ,  BARIK, Rajkishore ,  LIN, Tsung-Han ,  RAY, Joydeep ,  TANG, Ping T. ,  STRICKLAND, Michael S. ,  CHEN, Xiaoming ,  YAO, Anbang ,  SHPEISMAN, Tatiana ,  APPU, Abhishek R. ,  KOKER, Altug ,  AKHBARI, Farshad ,  SRINIVASA, Narayan ,  CHEN, Feng ,  KIM, Dukhwan ,  SATISH, Nadathur Rajagopalan ,  WEAST, John C. ,  MACPHERSON, Mike B. ,  HURD, Linda L. ,  RANGANATHAN, Vasanth ,  JAHAGIRDAR, Sanjeev S.

IPC: G06N3/045

CPC classification number: G06F15/78 ,  G06F9/30014 ,  G06F9/30036 ,  G06F1/3287 ,  G06F1/3293 ,  G06T15/005 ,  G06F15/76 ,  G06N3/084 ,  G06N3/063 ,  G06T1/20 ,  Y02D10/00 ,  G06N3/044 ,  G06N3/045

Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

公开(公告)号：EP3396532A2

公开(公告)日：2018-10-31

申请号：EP18162628.4

申请日：2018-03-19

Applicant: INTEL Corporation

Inventor： SINHA, Kamal ,  VEMBU, Balaji ,  NURVITADHI, Eriko ,  GALOPPO VON BORRIES, Nicolas C. ,  BARIK, Rajkishore ,  LIN, Tsung-Han ,  RAY, Joydeep ,  TANG, Ping T. ,  STRICKLAND, Michael S. ,  CHEN, Xiaoming ,  YAO, Anbang ,  SHPEISMAN, Tatiana ,  APPU, Abhishek R. ,  KOKER, Altug ,  AKHBARI, Farshad ,  SRINIVASA, Narayan ,  CHEN, Feng ,  KIM, Dukhwan ,  SATISH, Nadathur Rajagopalan ,  WEAST, John C. ,  MACPHERSON, Mike B. ,  HURD, Linda L. ,  RANGANATHAN, Vasanth ,  JAHAGIRDAR, Sanjeev S.

IPC: G06F9/30 ,  G06F15/78

CPC classification number: G06N3/063 ,  G06F1/3287 ,  G06F1/3293 ,  G06F9/30014 ,  G06F9/30036 ,  G06F15/76 ,  G06F15/78 ,  G06N3/04 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005

Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

公开(公告)号：EP3385837A1

公开(公告)日：2018-10-10

申请号：EP18159603.2

申请日：2018-03-01

Applicant: INTEL Corporation

Inventor： MA, Liwei ,  SATISH, Nadathur Rajagopalan ,  BOTTLESON, Jeremy ,  AKHBARI, Farshad ,  NURVITADHI, Eriko ,  APPU, Abhishek R. ,  KOKER, Altug ,  SINHA, Kamal ,  RAY, Joydeep ,  VEMBU, Balaji ,  RANGANATHAN, Vasanth ,  JAHAGIRDAR, Sanjeev

IPC: G06F9/448

CPC classification number: G06N3/08 ,  G06F9/4498 ,  G06N3/063 ,  G06T1/20

Abstract: A mechanism is described for facilitating fast data operations for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting input data to be used in computational tasks by a computation component of a compute pipeline of a processor including a graphics processor. The method may further include determining one or more frequently-used data values (FDVs) from the data, and pushing the one or more frequent data values to bypass the computational tasks.

公开(公告)号：EP2831691A1

公开(公告)日：2015-02-04

申请号：EP12872526.4

申请日：2012-03-30

Applicant: Intel Corporation

Inventor： CHHUGANI, Jatin ,  CK KIM, Changkyu ,  SATISH, Nadathur Rajagopalan

IPC: G06F1/00 ,  G06F9/22 ,  G06F9/30

CPC classification number: G06F7/36 ,  G06F7/32 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3005 ,  G06F9/3012 ,  G06F9/3867

Abstract: A semiconductor chip is described that includes an instruction execution unit having a functional unit, said functional unit having minimum and maximum comparison circuitry followed by interleaving circuitry, said minimum and maximum comparison circuitry to respectively identify minimums and maximums of same positioned elements from two different sets of sorted elements, said interleaving circuitry to interleave said minimums and maximums to help form a third sorted set composed of elements from said different sets and being larger than each of said different sets.

Abstract translation: 描述了一种半导体芯片，其包括具有功能单元的指令执行单元，所述功能单元具有最小和最大比较电路，随后是交错电路，所述最小和最大比较电路分别从两个不同集合中识别相同定位元素的最小值和最大值 所述交织电路交织所述最小值和最大值以帮助形成由来自所述不同集合的元素组成的第三有序集合，并且大于所述不同集合中的每一个集合。

公开(公告)号：EP4006723A3

公开(公告)日：2022-08-17

申请号：EP22152342.6

申请日：2018-03-01

Applicant: Intel Corporation

Inventor： MA, Liwel ,  SATISH, Nadathur Rajagopalan ,  BOTTLESON, Jeremy ,  AKHBARI, Farshad ,  NURVITADHI, Eriko ,  APPU, Abhishek R. ,  KOKER, Altug ,  SINHA, Kamal ,  RAY, Joydeep ,  VEMBU, Balaji ,  RANGANATHAN, Vasanth ,  JAHAGIRDAR, Sanjeev

IPC: G06F9/448 ,  G06T1/20

Abstract: A mechanism is described for facilitating fast data operations for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting input data to be used in computational tasks by a computation component of a compute pipeline of a processor including a graphics processor. The method may further include determining one or more frequently-used data values (FDVs) from the data, and pushing the one or more frequent data values to bypass the computational tasks.

公开(公告)号：EP3579103A1

公开(公告)日：2019-12-11

申请号：EP19183024.9

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： APPU, Abhishek R. ,  KOKER, Altug ,  HURD, Linda L. ,  KIM, Dukhwan ,  MACPHERSON, Mike B. ,  WEAST, John C. ,  CHEN, Feng ,  AKHBARI, Farshad ,  SRINIVASA, Narayan ,  SATISH, Nadathur Rajagopalan ,  TANG, Ping T. ,  RAY, Joydeep ,  STRICKLAND, Michael S. ,  CHEN, Xiaoming ,  YAO, Anbang ,  SHPEISMAN, Tatiana

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06T1/20 ,  G06N3/063

Abstract: A graphics processor and a method to perform a mixed precision multi-dimensional matrix multiply and accumulate operation is disclosed.

公开(公告)号：EP3396533A2

公开(公告)日：2018-10-31

申请号：EP18162635.9

申请日：2018-03-19

Applicant: INTEL Corporation

Inventor： NURVITADHI, Eriko ,  VEMBU, Balaji ,  GALOPPO VON BORRIES, Nicolas C. ,  BARIK, Rajkishore ,  LIN, Tsung-Han ,  SINHA, Kamal ,  SATISH, Nadathur Rajagopalan ,  BOTTLESON, Jeremy ,  AKHBARI, Farshad ,  KOKER, Altug ,  SRINIVASA, Narayan ,  KIM, Dukhwan ,  BAGHSORKHI, Sara S. ,  GOTTSCHLICH, Justin E. ,  CHEN, Feng ,  OULD-AHMED-VALL, Elmoustapha ,  NEALIS, Kevin ,  CHEN, Xiaoming ,  YAO, Anbang

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06T1/20 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/084

Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex machine learning compute operation.