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    SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS
    3.
    发明公开
    SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS 审中-公开
    系统维护工作人员培训

    公开(公告)号：EP3161616A2

    公开(公告)日：2017-05-03

    申请号：EP15815691.9

    申请日：2015-06-26

    Applicant: MicroUnity Systems Engineering, Inc.

    Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

    IPC: G06F9/30

    CPC classification number: G06F12/0875 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3895 ,  G06F2212/452

    Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

    Abstract translation: 公开了可扩展的宽操作，其中在执行指令中使用比处理器和存储器之间的数据路径更宽的操作数。 可扩展的宽操作数减少了执行计算的功能单元的设计中相关处理器的特性的影响，包括寄存器文件的宽度，处理器时钟速率，处理器的异常子系统以及加载中的操作顺序 并在宽缓存中使用操作数。

    VECTOR PROCESSING ENGINES EMPLOYING A TAPPED-DELAY LINE FOR FILTER VECTOR PROCESSING OPERATIONS, AND RELATED VECTOR PROCESSOR SYSTEMS AND METHODS
    4.
    发明公开
    VECTOR PROCESSING ENGINES EMPLOYING A TAPPED-DELAY LINE FOR FILTER VECTOR PROCESSING OPERATIONS, AND RELATED VECTOR PROCESSOR SYSTEMS AND METHODS 审中-公开
    随着对向量处理操作的抽头延迟线过滤器和相关的向量处理器的系统和方法的向量处理机

    公开(公告)号：EP3069237A1

    公开(公告)日：2016-09-21

    申请号：EP14819132.3

    申请日：2014-11-13

    Applicant: Qualcomm Incorporated

    Inventor： KHAN, Raheel ,  MUJAHID, Fahad Ali ,  SHIRAVI, Afshin

    IPC: G06F9/38 ,  G06F15/80

    CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/3887 ,  G06F9/3895 ,  G06F15/8053

    Abstract: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption are disclosed. Related vector processor systems and methods are also disclosed. The VPEs are configured to provide filter vector processing operations. To minimize re-fetching of input vector data samples from memory to reduce power consumption, a tapped-delay line(s) is included in the data flow paths between a vector data file and execution units in the VPE. The tapped-delay line(s) is configured to receive and provide input vector data sample sets to execution units for performing filter vector processing operations. The tapped-delay line(s) is also configured to shift the input vector data sample set for filter delay taps and provide the shifted input vector data sample set to execution units, so the shifted input vector data sample set does not have to be re-fetched during filter vector processing operations.

    Data input system for macro activation
    6.
    发明公开
    Data input system for macro activation 审中-公开
    Eingabesystem von Makro-Aktivierung

    公开(公告)号：EP2942708A1

    公开(公告)日：2015-11-11

    申请号：EP14179990.8

    申请日：2014-08-06

    Applicant: Giga-Byte Technology Co., Ltd.

    Inventor： Lin, Yin Yu ,  Shih, Po-Jen

    IPC: G06F3/16 ,  G10L15/22 ,  G06F9/44

    CPC classification number: G06F9/3017 ,  G06F3/167 ,  G06F9/3895 ,  G06F9/451

    Abstract: An input system of macro activation for rapidly activating a pre-recorded macro procedure includes a memory module, an input recognition module, a data processing unit, and a macro-processing unit. The memory module stores at least one recognition sample and a macro-activating command corresponding to the recognition sample. The input recognition module is used to read in a data to be recognized. The data processing unit receives the data to be recognized and determines whether the data to be recognized matches the recognition sample. If the data to be recognized matches the recognition sample, the data processing unit retrieves the macro-activating command from the memory module and issues the macro-activating command to the macro-processing unit, which is connected to the data processing unit. The macro-processing unit performs the pre-recorded macro procedure upon receiving the macro-activating command.

    Abstract translation: 用于快速激活预先记录的宏程序的宏激活输入系统包括存储器模块，输入识别模块，数据处理单元和宏处理单元。 存储器模块存储与识别样本相对应的至少一个识别样本和宏激活命令。 输入识别模块用于读取要识别的数据。 数据处理单元接收要识别的数据，并确定要识别的数据是否与识别样本相匹配。 如果要识别的数据与识别样本相匹配，则数据处理单元从存储器模块检索宏激活命令，并将宏命令发送到连接到数据处理单元的宏处理单元。 宏处理单元在接收到宏激活命令时执行预先记录的宏程序。

    VECTOR PROCESSING ENGINE EMPLOYING DESPREADING CIRCUITRY IN DATA FLOW PATHS BETWEEN EXECUTION UNITS AND VECTOR DATA MEMORY, AND RELATED METHOD
    8.
    发明公开
    VECTOR PROCESSING ENGINE EMPLOYING DESPREADING CIRCUITRY IN DATA FLOW PATHS BETWEEN EXECUTION UNITS AND VECTOR DATA MEMORY, AND RELATED METHOD 审中-公开
    WITH间竣工单位和矢量数据存储以及相应方法，在数据流路径，电路解扩向量处理器

    公开(公告)号：EP3069236A1

    公开(公告)日：2016-09-21

    申请号：EP14812019.9

    申请日：2014-11-07

    Applicant: Qualcomm Incorporated

    Inventor： KHAN, Raheel

    IPC: G06F9/38 ,  G06F15/80

    CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/3887 ,  G06F9/3895 ,  G06F9/3897 ,  G06F15/8053 ,  G06F17/10

    Abstract: Vector processing engines (VPEs) employing despreading circuitry in data flow paths between execution units and vector data memory to provide in-flight despreading of spread-spectrum sequences. Related vector processing instructions, systems, and methods are also disclosed. Despreading circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The despreading circuitry is configured to despread spread-spectrum sequences using an output vector data sample set from execution units in-flight while the output vector data sample set is being provided over the output data flow paths from the execution units to the vector data memory. In-flight despreading of output vector data sample sets means that the output vector data sample set provided by execution units is despread before being stored in vector data memory, so that the output vector data sample set is stored in the vector data memory in a despread format.

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