公开(公告)号：EP3543845A3

公开(公告)日：2019-12-11

申请号：EP19166050.5

申请日：2018-03-14

Applicant: Intel Corporation

Inventor： OULD-AHMED-VALL, Elmoustapha ,  LAKSHMANAN, Barath ,  SHPEISMAN, Tatiana ,  RAY, Joydeep ,  TANG, Ping T. ,  STRICKLAND, Michael ,  CHEN, Xiaoming ,  YAO, Anbang ,  ASHBAUGH, Ben J. ,  HURD, Linda L. ,  MA, Liwei

IPC: G06F9/30 ,  G06F9/38 ,  G06T15/00 ,  G06F13/40

Abstract: A general-purpose graphics processing unit is described. The graphics processing unit includes a streaming multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading, wherein the streaming multiprocessor comprises a first processing block including a first processing core having a first floating-point data path and a second processing core having a first integer data path, the first integer data path independent of the first floating-point data path, wherein the first integer data path is to enable execution of a first instruction and the first floating-point data path is to enable execution of a second instruction, the first instruction to be executed concurrently with the second instruction; a second processing block including a third processing core having a second floating-point data path and a fourth processing core having a second integer data path, the second integer data path independent of the second floating-point data path, wherein the second integer data path is to enable execution of a third instruction and the second floating-point data path is to enable execution of a fourth instruction, the third instruction to be executed concurrently with the fourth instruction; and a memory coupled with the first processing block and the second processing block.

公开(公告)号：EP3396532A3

公开(公告)日：2019-03-13

申请号：EP18162628.4

申请日：2018-03-19

Applicant: INTEL Corporation

Inventor： SINHA, Kamal ,  VEMBU, Balaji ,  NURVITADHI, Eriko ,  GALOPPO VON BORRIES, Nicolas C. ,  BARIK, Rajkishore ,  LIN, Tsung-Han ,  RAY, Joydeep ,  TANG, Ping T. ,  STRICKLAND, Michael S. ,  CHEN, Xiaoming ,  YAO, Anbang ,  SHPEISMAN, Tatiana ,  APPU, Abhishek R. ,  KOKER, Altug ,  AKHBARI, Farshad ,  SRINIVASA, Narayan ,  CHEN, Feng ,  KIM, Dukhwan ,  SATISH, Nadathur Rajagopalan ,  WEAST, John C. ,  MACPHERSON, Mike B. ,  HURD, Linda L. ,  RANGANATHAN, Vasanth ,  JAHAGIRDAR, Sanjeev S.

IPC: G06F9/30 ,  G06F15/78 ,  G06F1/32 ,  G06T15/00

Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

公开(公告)号：EP3234785A1

公开(公告)日：2017-10-25

申请号：EP15870620.0

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： LEWIS, Brian T. ,  BARIK, Rajkishore ,  SHPEISMAN, Tatiana

IPC: G06F13/12 ,  G06F13/16

CPC classification number: G06F9/544 ,  G06T1/20

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.

Abstract translation: 通常，本公开提供用于在第一处理器（例如，GPU）和第二处理器（例如，CPU）之间实现功能回调请求的系统，设备，方法和计算机可读介质。 该系统可以包括耦合到第一和第二处理器的共享虚拟存储器（SVM），该SVM被配置为存储至少一个双端队列（Deque）。 第一处理器的执行单元（EU）可以与第一Deques相关联并且被配置为将回调请求推送到该第一Deque。 在第二处理器上执行的请求处理程序线程可以被配置为：弹出来自第一Deque的回调请求中的一个; 执行由弹出的回调请求指定的函数; 并响应该功能的完成而向EU产生完成信号。

公开(公告)号：EP2691852A1

公开(公告)日：2014-02-05

申请号：EP11862620.9

申请日：2011-12-09

Applicant: Intel Corporation

Inventor： NI, Yang ,  BARIK, Rajkishore ,  ADL-TABATABAI, Ali-Reza ,  SHPEISMAN, Tatiana ,  RAO, Jayanth N. ,  ASHBAUGH, Ben J. ,  JANCZAK, Tomasz

IPC: G06F9/06 ,  G06F9/45 ,  G06F13/14

CPC classification number: G06F12/0806 ,  G06F15/167 ,  G06T1/60

Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

公开(公告)号：EP1763750A1

公开(公告)日：2007-03-21

申请号：EP05759575.3

申请日：2005-06-10

Applicant: Intel Corporation

Inventor： SHPEISMAN, Tatiana ,  ADL-TABATABAI, Ali-Reza ,  MURPHY, Brian

IPC: G06F9/52 ,  G06F9/45

CPC classification number: G06F9/528 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/52 ,  Y10S707/99938

Abstract: Thread synchronization with lock inflation methods and apparatus for managed run-time environments are disclosed. An example method disclosed herein comprises determining a locking operation to perform on a lock corresponding to the object, performing an optimistically balanced synchronization of the lock if the locking operation is not unbalanced, and modifying a lock shape of the lock if the locking operation is unbalanced.

公开(公告)号：EP1751659A1

公开(公告)日：2007-02-14

申请号：EP04781238.3

申请日：2004-08-13

Applicant: Intel Corporation

Inventor： ADL-TABATABAI, Ali-Reza ,  SHPEISMAN, Tatiana ,  MURPHY, Brian

IPC: G06F9/46

CPC classification number: G06F9/52 ,  Y10S707/99938

Abstract: Thread synchronization methods and apparatus for managed run-time environments are disclosed. An example method disclosed herein comprises determining a set of locking operations to perform on a lock corresponding to an object, performing an initial locking operation comprising at least one of a balanced synchronization of the lock and an optimistically balanced synchronization of the lock if the initial locking operation is not unbalanced, and, if the initial locking operation is active and comprises the optimistically balanced synchronization, further comprising modifying a state of a pending optimistically balanced release corresponding to the optimistically balanced synchronization if a subsequent locking operation is unbalanced.

公开(公告)号：EP4242838A3

公开(公告)日：2023-09-27

申请号：EP23182458.2

申请日：2018-03-26

Applicant: INTEL Corporation

Inventor： KAUL, Himanshu ,  ANDERS, Mark A. ,  MATHEW, Sanu K. ,  YAO, Anbang ,  RAY, Joydeep ,  TANG, Ping T. ,  STRICKLAND, Michael S. ,  CHEN, Xiaoming ,  SHPEISMAN, Tatiana ,  APPU, Abhishek R. ,  KOKER, Altug ,  SINHA, Kamal ,  VEMBU, Balaji ,  GALOPPO VON BORRIES, Nicolas C. ,  NURVITADHI, Eriko ,  BARIK, Rajkishore ,  LIN, Tsung-Han ,  RANGANATHAN, Vasanth ,  JAHAGIRDAR, Sanjeev

IPC: G06F7/544 ,  G06F9/30 ,  G06F7/483 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08

Abstract: One embodiment provides for a processing unit comprising fetch and decode circuitry to fetch and decode a floating-point multiply-accumulate instruction; and execution circuitry to execute the floating-point multiply-accumulate instruction. The execution circuitry comprises mantissa multiplication circuitry, wherein the mantissa multiplication circuitry is shared with an integer datapath of the execution circuitry, wherein responsive to the floating-point multiply-accumulate instruction, the mantissa multiplication circuitry is to perform a multiplication operation with a mantissa value of each 16-bit floating-point data element of a first plurality of 16-bit floating-point data elements and a mantissa value of a corresponding 16-bit floating-point data element of a second plurality of 16-bit floating-point data elements to generate a corresponding plurality of mantissa results; exponent processing circuitry, responsive to the floating-point multiply-accumulate instruction, to perform an operation with an exponent value of each 16-bit floating-point data element of the first plurality of 16-bit floating-point data elements and an exponent value of each corresponding 16-bit floating-point data element of the second plurality of 16-bit floating-point data elements to generate a corresponding plurality of exponent results; circuitry to process the plurality of mantissa results and the plurality of exponent results to generate a corresponding floating-point product; and adder circuitry to generate a plurality of result floating-point values, each result floating-point value comprising a sum of one or more floating-point products of the plurality of floating-point products and a corresponding accumulated floating-point value of a plurality of accumulated floating-point values.

公开(公告)号：EP3396530B1

公开(公告)日：2020-12-02

申请号：EP18161820.8

申请日：2018-03-14

Applicant: Intel Corporation

Inventor： OULD-AHMED-VALL, Elmoustapha ,  LAKSHMANAN, Barath ,  SHPEISMAN, Tatiana ,  RAY, Joydeep ,  TANG, Ping T. ,  STRICKLAND, Michael ,  CHEN, Xiaoming ,  YAO, Anbang ,  ASHBAUGH, Ben J. ,  HURD, Linda L. ,  MA, Liwei

IPC: G06F9/30 ,  G06T1/20

公开(公告)号：EP3579103A1

公开(公告)日：2019-12-11

申请号：EP19183024.9

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： APPU, Abhishek R. ,  KOKER, Altug ,  HURD, Linda L. ,  KIM, Dukhwan ,  MACPHERSON, Mike B. ,  WEAST, John C. ,  CHEN, Feng ,  AKHBARI, Farshad ,  SRINIVASA, Narayan ,  SATISH, Nadathur Rajagopalan ,  TANG, Ping T. ,  RAY, Joydeep ,  STRICKLAND, Michael S. ,  CHEN, Xiaoming ,  YAO, Anbang ,  SHPEISMAN, Tatiana

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06T1/20 ,  G06N3/063

Abstract: A graphics processor and a method to perform a mixed precision multi-dimensional matrix multiply and accumulate operation is disclosed.

公开(公告)号：EP3396524A1

公开(公告)日：2018-10-31

申请号：EP18164093.9

申请日：2018-03-26

Applicant: INTEL Corporation

Inventor： KAUL, Himanshu ,  ANDERS, Mark A. ,  MATHEW, Sanu K. ,  YAO, Anbang ,  RAY, Joydeep ,  TANG, Ping T. ,  STRICKLAND, Michael S. ,  CHEN, Xiaoming ,  SHPEISMAN, Tatiana ,  APPU, Abhishek R. ,  KOKER, Altug ,  SINHA, Kamal ,  VEMBU, Balaji ,  GALOPPO VON BORRIES, Nicolas C. ,  NURVITADHI, Eriko ,  BARIK, Rajkishore ,  LIN, Tsung-Han ,  RANGANATHAN, Vasanth ,  JAHAGIRDAR, Sanjeev

IPC: G06F7/483 ,  G06F7/544 ,  G06F9/30

CPC classification number: G09G5/363 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F2207/3824 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N99/005 ,  G06T1/20 ,  G06T15/005 ,  G09G5/393

Abstract: One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.