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1.发明公开Method for producing semiconductor devices including the use of reactive ion etching 失效用于生产包括使用反应性离子蚀刻的半导体器件的方法
公开(公告)号：EP0068275A3
公开(公告)日：1986-10-01
申请号：EP82105210
申请日：1982-06-15
发明人： Anantha, Narasipur Gundappa , Bhatia, Harsaran Singh , Mauer IV, John Lester , Sarkary, Homi Gustadji
IPC分类号： H01L21/76 , H01L21/306
CPC分类号： H01L21/76224 , H01L21/31055 , H01L21/31116 , H01L21/76202 , Y10S438/978
摘要： The method comprises blanket depositing a layer of a first material on a semiconductor structure, on the surface of which protruding regions (34A) have been formed bordering with a vertical wall (40) on adjacent areas, and subsequently removing completely or selectively that layer by reactive ion etching where prior to the deposition of said layer the vertical wall (40) is reshaped either by removing material from that wall (40) or by accumulating a second material on said wall (40). The method prevents that uncontrolled residues of materials like a doped polysilicon after reactive ion etching steps. These residues might be detrimental to devices and elements, like transistors and resistors formed in the semiconductor substrate.
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2.发明授权
公开(公告)号：EP0026276B1
公开(公告)日：1983-11-30
申请号：EP80103971.0
申请日：1980-07-10
发明人： Anantha, Narasipur Gundappa , Cavaliere, Joseph Richard , Konian, Richard Robert , Srinivasan, Gurumakonda, Ramaswamiengar , Stoller, Herbert Ivan , Walsh, James Leo
CPC分类号： H01L21/033 , H01L29/0826 , H01L29/1004 , Y10S148/131 , Y10S148/141
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公开(公告)号：EP0036500B1
公开(公告)日：1983-08-31
申请号：EP81101368.9
申请日：1981-02-25
CPC分类号： H01L29/66143 , H01L21/0337 , H01L29/872
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4.发明授权
公开(公告)号：EP0032211B1
公开(公告)日：1987-09-02
申请号：EP80107863.5
申请日：1980-12-12
IPC分类号： H01L21/268 , H01L29/04 , H01L21/20 , H01L21/312
CPC分类号： H01L21/02675 , H01L21/02271 , H01L21/2026 , H01L21/268 , H01L21/312 , H01L21/76248 , H01L29/04 , Y10S148/092 , Y10S148/123 , Y10S148/138
摘要： The method starts from a monocrystalline semiconductor substrate (2) having a highly doped region (1), and being covered by an oxide mask (3) which is apertured above region (1). A layer (6) of polysilicon is deposited over oxide mask (3). The structure is exposed to laser radiation (14) to convert layer (6) into monocrystalline silicon within and above the oxide apertures. … The method is useful in making filamentary pedestal transistors without extrinsic base-collector junctions. In this present case, region (1) serves as a subcollector, two polycrystalline areas are made monocrystalline, with the one area(4) and the polycrystalline area (7) surrounding it being doped with a base dopant, and the other area (5) being made the collector reach-through region. The upper portion (10) of area (4) is made the emitter.
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5.发明公开Method for fabricating vertical NPN and lateral PNP transistors in the same semiconductor body 失效一种用于在相同的半导体本体制造垂直NPN和横向PNP晶体管的过程。
公开(公告)号：EP0137906A1
公开(公告)日：1985-04-24
申请号：EP84106535.2
申请日：1984-06-08
CPC分类号： H01L29/6625 , H01L21/743 , H01L21/8224 , H01L29/735 , Y10S148/01
摘要： The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body (22) having a buried N + region (21) within the body. A P type emitter region (94) is located in the body. An N type base region (68) is located around the side periphery of the emitter region (94). A P type collector region is located in the body surrounding the periphery of the base region (68). A first P + polycrystalline silicon layer (64) is located on the surface of the body (22) to make physical and electrical contact with the collector region. A second P + polycrystalline silicon layer (90) acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A vertical insulator layer (70) on the edge of the first polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region (68) at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region (24) extending from the surface of the body (22) to the buried N+ region (21) acts as an electrical contact through the N+ buried layer to the base region (68). The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter (94) formed around the periphery of a channel or groove which has at its base a insulating layer (84) such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.
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6.发明授权
公开(公告)号：EP0001574B1
公开(公告)日：1982-01-13
申请号：EP78101028.5
申请日：1978-09-29
CPC分类号： H01L21/743 , H01L21/76224 , H01L27/0802 , H01L29/8605
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7.发明授权
公开(公告)号：EP0001550B1
公开(公告)日：1981-10-07
申请号：EP78100830.5
申请日：1978-09-06
CPC分类号： H01L21/033 , H01L21/2257 , H01L21/76229 , H01L23/53271 , H01L29/0649 , H01L29/42304 , H01L2924/0002 , Y10S148/051 , Y10S148/122 , Y10S148/131 , H01L2924/00
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8.发明公开Verfahren zum Herstellen eines lateralen PNP- oder NPN-Transistors mit hoher Verstärkung und dadurch hergestellter Transistor 失效制造具有高增益和由此产生晶体管横向PNP或NPN晶体管的方法。
公开(公告)号：EP0005728A1
公开(公告)日：1979-12-12
申请号：EP79101267.7
申请日：1979-04-26
发明人： Anantha, Narasipur Gundappa , Bhatia, Harsaran Singh , Gaur, Santosh Prasad , Pogge, Hans Bernhard
CPC分类号： H01L27/0821 , H01L21/76232 , H01L29/735 , Y10S148/031 , Y10S148/051 , Y10S148/085
摘要： Verfahren zum Herstellen lateraler PNP- oder NPN-Transistoren in isolierten, monokristallinen Siliciumbereichen, die durch Siliciumdioxid-Isolationszonen isoliert sind, wobei die PNP- oder NPN-Transistoren innerhalb der isolierten monokristallinen Zone teilweise unterhalb der Oberfläche des Halbleiters gebildet werden. Die P-Emitter oder N-Emitterdiffusion wird über dem Abschnitt der Siliciumdioxid-Schicht durchgeführt, die sich teilweise in die isolierte monokristalline Zone hinein erstreckt. Durch diesen Aufbau wird die vertikale Strominjektion herabgesetzt, so daß man eine relativ hohe (Beta) Verstärkung selbst bei kleinen Basis-Emitter-Spannungen erhält. Der durch dieses Verfahren erzeugte laterale PNP- oder NPN-Transistor liegt in einer isolierten monokristallinen Siliciumzone, wobei die Siliciumdioxid-Isolation die Zone umgibt und teilweise unterhalb der Oberfläche in die isolierte monokristalline Siliciumzone hineinreicht. Die P-Emitter- oder N-Emitter-Diffusion liegt über dem Abschnitt der Siliciumdioxid-Schicht, der sich teilweise in die monokristalline isolierte Zone hineinerstreckt.
摘要翻译： 在所述分离的单晶硅区域，其通过二氧化硅隔离区绝缘，其中所述PNP或NPN晶体管被分离的单晶区部分内的半导体的表面下方形成的制造横向PNP或NPN晶体管的方法。 P型发射极和N型发射极扩散在二氧化硅层，其在所述分离的单晶区内部部分延伸的部分执行。 通过这种结构中，垂直电流注入被减少，使得相对高的（测试版）接收甚至具有小基极 - 发射极电压增益。 由该方法生产的横向PNP或NPN晶体管处于绝缘单晶硅区，所述周围区域并且部分地二氧化硅绝缘表面的下方在所述分离的单晶硅区延伸。 在p-发射极或N极 - 发射极扩散超过二氧化硅层，其部分地延伸到所述单晶分离区域的该部分。
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公开(公告)号：EP0072412A3
公开(公告)日：1984-04-25
申请号：EP82105757
申请日：1982-06-29
CPC分类号： H01L27/1023 , G11C11/34 , H01L27/1028 , H01L27/115
摘要： A dynamic memory cell has a P+ injector region (48) surrounded by an N+ region (44) in an N- layer (30) on an N+ layer (20). The injector region (48) is placed between N+ source and drain regions (38, 40). Holes injected into the N-layer (30) are trapped by the high-low junctions at the N+, N- interfaces and are detected by sensing the source-drain current. Current levels are used to establish binary one and zero levels in the cell. Four masks in an aligned procedure simplify fabrication.
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公开(公告)号：EP0072412A2
公开(公告)日：1983-02-23
申请号：EP82105757.7
申请日：1982-06-29
CPC分类号： H01L27/1023 , G11C11/34 , H01L27/1028 , H01L27/115
摘要： A dynamic memory cell has a P+ injector region (48) surrounded by an N+ region (44) in an N- layer (30) on an N+ layer (20). The injector region (48) is placed between N+ source and drain regions (38, 40). Holes injected into the N-layer (30) are trapped by the high-low junctions at the N+, N- interfaces and are detected by sensing the source-drain current. Current levels are used to establish binary one and zero levels in the cell. Four masks in an aligned procedure simplify fabrication.
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