公开(公告)号：EP0065133A2

公开(公告)日：1982-11-24

申请号：EP82103562.3

申请日：1982-04-27

申请人： International Business Machines Corporation

发明人： Anantha, Narasipur Gundappa ,  Bhatia, Harsaran Singh ,  Gaur, Santosh Prasad ,  Mauer IV, John Lester

IPC分类号： H01L29/91

CPC分类号： H01L29/872

摘要： The Schottky barrier diode having a self-aligned guard ring comprises a dielectric layer (3) on a silicon substrate said layer (3) having a substantially vertically walled hole therein, a doped silicon lining (5) being of uniform width covering the silicon along the walls of said hole and contact metal (7) on said substrate exposed within the inner perimeter of that lining (5).
To produce such a diode a hole ist etched anisotropically into a dielectric layer (3) on a silicon substrate. Then a doped silicon layer (4) is deposited which is reactively ion etched, to expose said substrate through said hole. By heating the dopant in the remainder of said silicon layer (4) is diffused into the substrate. Onto the exposes substrate metal (7) is applied.

摘要翻译： 具有自对准保护环的肖特基势垒二极管包括在硅衬底上的介电层（3），所述层（3）上具有基本上垂直的壁孔，掺杂硅衬层（5）具有均匀的宽度，覆盖硅 所述孔的壁和所述基底上的接触金属（7）暴露在该衬里（5）的内周边内。 为了制造这样的二极管，将各向异性地蚀刻到硅衬底上的电介质层（3）中的孔。 然后沉积掺杂的硅层（4），其被反应离子蚀刻，以通过所述孔暴露所述衬底。 通过加热所述硅层（4）的其余部分中的掺杂剂扩散到衬底中。 在曝光的基底金属（7）上施加。

公开(公告)号：EP0073370A3

公开(公告)日：1986-06-11

申请号：EP82107225

申请日：1982-08-10

申请人： International Business Machines Corporation

发明人： Joy, Richard Carleton ,  Kemlage, Bernard Michael ,  Mauer IV, John Lester

IPC分类号： H01L21/76 ,  H01L21/74

CPC分类号： H01L21/76202 ,  H01L21/743 ,  H01L21/763

摘要： An integrated circuit structure having substrate contacts formed as a part of the isolation structure and method for making the same is described. The integrated circuit structure is composed of a monocrystalline silicon body (2, 4) having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion (22, 24) at and just below the surface of the integrated circuit and a deep portion which extends from the side of the recessed dielectric portion opposite to that portion at the surface of said body into the monocrystalline silicon body. A highly doped polycrystalline silicon substrate contact (20) is located within the deep portion of the pattern of isolation. At certain locations the deep portion of the pattern extends to the surface of the silicon body where interconnection metallurgy can electrically contact the polycrystalline silicon so as to form a substrate contact to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

摘要翻译： 描述了具有形成为隔离结构的一部分的衬底触点的集成电路结构及其制造方法。 集成电路结构由单体硅体（2,4）构成，单体硅体（2,4）具有围绕体内单晶硅区域的介电隔离图形。 电介质隔离图案包括位于集成电路表面正下方的凹陷电介质部分（22,24），以及从凹陷电介质部分的与所述主体表面处的该部分相反的一侧延伸进入 单晶硅体。 高度掺杂的多晶硅衬底触点（20）位于隔离图案的深部内。 在某些位置，图案的深部延伸到硅本体的表面，在该表面处，互连冶金可以与多晶硅电接触，从而形成到隔离件深部底部的衬底触点，其中触点电连接到 硅体。 多种集成电路器件结构中的任何一种可以被结合在单晶硅区域内。 这些器件包括双极型晶体管，场效应晶体管，电容器，二极管，电阻器等。

公开(公告)号：EP0072966A3

公开(公告)日：1986-06-11

申请号：EP82107226

申请日：1982-08-10

申请人： International Business Machines Corporation

发明人： Joy, Richard Carleton ,  Kemlage, Bernard Michael ,  Mauer IV, John Lester

IPC分类号： H01L21/76 ,  H01L21/74

CPC分类号： H01L21/763 ,  H01L21/743 ,  H01L21/76202

摘要： An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body (2, 4) having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion (14) at and just below the surface of the integrated circuit and a deep portion (30) which extends through the recessed dielectric portion (14) and extends further into the monocrystalline silicon body (2, 4) than the recessed portion. A highly doped polycrystalline silicon substrate contact (30) is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

公开(公告)号：EP0072966B1

公开(公告)日：1989-03-08

申请号：EP82107226.1

申请日：1982-08-10

申请人： International Business Machines Corporation

发明人： Joy, Richard Carleton ,  Kemlage, Bernard Michael ,  Mauer IV, John Lester

IPC分类号： H01L21/76 ,  H01L21/74

CPC分类号： H01L21/763 ,  H01L21/743 ,  H01L21/76202

公开(公告)号：EP0068275A3

公开(公告)日：1986-10-01

申请号：EP82105210

申请日：1982-06-15

申请人： International Business Machines Corporation

发明人： Anantha, Narasipur Gundappa ,  Bhatia, Harsaran Singh ,  Mauer IV, John Lester ,  Sarkary, Homi Gustadji

IPC分类号： H01L21/76 ,  H01L21/306

CPC分类号： H01L21/76224 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76202 ,  Y10S438/978

摘要： The method comprises blanket depositing a layer of a first material on a semiconductor structure, on the surface of which protruding regions (34A) have been formed bordering with a vertical wall (40) on adjacent areas, and subsequently removing completely or selectively that layer by reactive ion etching where prior to the deposition of said layer the vertical wall (40) is reshaped either by removing material from that wall (40) or by accumulating a second material on said wall (40). The method prevents that uncontrolled residues of materials like a doped polysilicon after reactive ion etching steps. These residues might be detrimental to devices and elements, like transistors and resistors formed in the semiconductor substrate.

公开(公告)号：EP0072966A2

公开(公告)日：1983-03-02

申请号：EP82107226.1

申请日：1982-08-10

申请人： International Business Machines Corporation

发明人： Joy, Richard Carleton ,  Kemlage, Bernard Michael ,  Mauer IV, John Lester

IPC分类号： H01L21/76 ,  H01L21/74

CPC分类号： H01L21/763 ,  H01L21/743 ,  H01L21/76202

摘要： An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body (2, 4) having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion (14) at and just below the surface of the integrated circuit and a deep portion (30) which extends through the recessed dielectric portion (14) and extends further into the monocrystalline silicon body (2, 4) than the recessed portion. A highly doped polycrystalline silicon substrate contact (30) is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

公开(公告)号：EP0499050A1

公开(公告)日：1992-08-19

申请号：EP92100895.9

申请日：1992-01-21

申请人： International Business Machines Corporation

发明人： D'Heurle, Francois ,  Harper, James McKell ,  Mauer IV, John Lester

IPC分类号： H01L21/90 ,  H01L21/321

CPC分类号： H01L21/321 ,  H01L21/3212 ,  H01L21/76877 ,  Y10S148/13

摘要： A method for filling VLSI high aspect ratio vias and lines in VLSI interconnection structures, with a low resistivity metal at temperatures below 400°C. A low melting point alloy (20) of a desired low resistivity metal is deposited into the high aspect ratio vias or lines. The alloy (20) is then purified in place by bringing the alloying element to the surface of the deposited alloy and removing the element from said surface thereby leaving the low resistivity metal in the interconnection structure. In one embodiment, the alloy is purified by using a low temperature oxidation process to allow the alloying element to diffuse to the surface of the deposited alloy where a surface oxide (28) is formed. The surface oxide is then removed by chemical etching or by chemical mechanical polishing. In a second embodiment, a continuous exposure to a plasma etching or reactive ion etching will steadily remove the alloying element from the surface of the deposited alloy. In a third embodiment, the deposited alloy is planarized and then a sink layer is deposited onto the planarized interconnection structure. The structure is annealed in order to allow the alloying element to diffuse into the sink layer. The sink layer is then removed by chemical mechanical polishing.

摘要翻译： 一种用于填充VLSI高纵横比的通孔和线在VLSI互连结构，其中在低于400所需的低电阻率金属的℃的低熔点合金（20）的温度低的电阻率金属的方法沉积到高纵横比的通孔 或线条。 合金（20）然后在适当位置通过使合金元素到所沉积的合金的表面和去除从所述表面的元件，从而留下在互连结构中的低电阻率金属纯化。 在一个中，实施例合金是通过使用低温氧化工艺，以允许合金元素扩散到沉积的合金，其中的表面氧化（28）形成的表面进行纯化。 表面氧化，然后通过化学蚀刻或通过化学机械抛光除去。 在第二实施例中，连续暴露于等离子体蚀刻或反应性离子蚀刻将稳步从沉积的合金的表面上除去合金元素。 在第三实施例中，沉积的合金被平坦化，然后沉层沉积在平面化的互连结构。 为了使合金元素扩散到吸收层的结构进行退火。 信宿层然后由化学机械抛光除去。

公开(公告)号：EP0046525A3

公开(公告)日：1984-07-25

申请号：EP81106121

申请日：1981-08-05

申请人： International Business Machines Corporation

发明人： Logan, Joseph Skinner ,  Mauer IV, John Lester ,  Rothman, Laura Beth ,  Schwartz, Geraldine Cogin ,  Standley, Charles Lambert

IPC分类号： H01L23/52 ,  H01L21/90 ,  H01L23/54

CPC分类号： H01L23/5226 ,  H01L21/4846 ,  H01L21/7688 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S438/951 ,  H01L2924/00

摘要： The package has at least two levels of conductive interconnected patterns (26, 50A. 50B). The insulation containing the metal filled via openings (36) between the different levels consists of a lower layer (30) of an electrically insulating organic polymer and an overlying oxygen plasma resistant inorganic insulating layer (23). In the formation of the interconnection metallurgy inorganic insulating layer (23) prohibits overetching in producing the hole pattern in the organic insulating layer (42) laterally surrounding the conductive pattern (50A, 50B) in the next level. The entirety of the insulation between the levels is thus ensured.

公开(公告)号：EP0068275A2

公开(公告)日：1983-01-05

申请号：EP82105210.7

申请日：1982-06-15

申请人： International Business Machines Corporation

发明人： Anantha, Narasipur Gundappa ,  Bhatia, Harsaran Singh ,  Mauer IV, John Lester ,  Sarkary, Homi Gustadji

IPC分类号： H01L21/76 ,  H01L21/306

CPC分类号： H01L21/76224 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76202 ,  Y10S438/978

摘要： The method comprises blanket depositing a layer of a first material on a semiconductor structure, on the surface of which protruding regions (34A) have been formed bordering with a vertical wall (40) on adjacent areas, and subsequently removing completely or selectively that layer by reactive ion etching where prior to the deposition of said layer the vertical wall (40) is reshaped either by removing material from that wall (40) or by accumulating a second material on said wall (40).
The method prevents that uncontrolled residues of materials like a doped polysilicon after reactive ion etching steps. These residues might be detrimental to devices and elements, like transistors and resistors formed in the semiconductor substrate.

摘要翻译： 该方法包括在半导体结构上覆盖一层第一材料，其表面上已经形成有与相邻区域上的垂直壁（40）邻接的突出区域（34A），并随后通过 反应离子蚀刻，其中在沉积所述层之前，垂直壁（40）通过从该壁（40）去除材料或通过在第二壁（40）上积累第二材料来重塑。 该方法在反应离子蚀刻步骤之后，防止诸如掺杂多晶硅的材料的不受控制的残留物。 这些残留物可能不利于器件和元件，如在半导体衬底中形成的晶体管和电阻器。

公开(公告)号：EP0571727A1

公开(公告)日：1993-12-01

申请号：EP93104231.1

申请日：1993-03-16

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Blauner, Patricia G. ,  Dubner, Andrew David ,  Levin, James Peter ,  Longo, Peter Paul ,  Mauer IV, John Lester ,  Wagner, Alfred

IPC分类号： H01J37/317

CPC分类号： H01J37/3178

摘要： The disclosure describes a method and structure to control the focussed ion beam induced deposition of material. The structure includes a focussed ion beam which is directed onto a target surface. The ion beam is deflected to locations on the target surface and is blanked and unblanked at desired intervals. The deflection and blanking are controlled by timing means in response to computer signals. A precursor gas is adsorbed into the target surface and the ion beam selectively decomposes the adsorbed gas along a desired shape to provide material deposition. The shape of the deposition is specified by a number of successive beam spots. The spots can be specified to overlap adjacent spots if desired for better edge resolution, but in general, the optimum yield is obtained without overlap. The dwell time for each spot is set to provide high net yield for the deposited material. The beam is stepped to each position in the shape and the deposition is repeated. Alternatively, the beam could be moved in sequential line scans either stepwise or continuously between spots, but spot by spot deflection allows better control of the feature shape. After completing all the spots in the pattern, the process is repeated until a film of material of the desired thickness is built up.

摘要翻译： 本发明描述的方法和结构，以控制材料的聚焦离子束诱导沉积。 该结构包括聚焦离子束的所有被引导到目标表面上。 该离子束被偏转到目标表面上的位置和被消隐和以期望的间隔未被阻断。 偏转和消隐是通过响应于计算机信号的定时装置来控制。 前体气体被吸附到目标表面和离子束选择性地分解吸附的气体沿着所希望的形状，以提供材料的沉积。 沉积的形状是由多个连续的束点的指定。 斑点可以指定重叠相邻光斑如果需要清除为更好的边缘分辨率，但在一般情况下，最佳的产率没有重叠得到。 每个点的停留时间被设置为提供高的净产量为所沉积的材料。 波束步进到的形状的每个位置，并且重复该沉积。 可替换地，光束能以顺序线移动扫描阶段性或连续性点之间，但光点通过点偏转允许特征形状的更好控制。 完成在图案中的所有斑点之后，重复该过程，直到所希望的厚度的材料制成的膜被建立起来了。