利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

36 条记录 (耗时 0.013 秒)

    Complementary metal oxide silicon (CMOS) device structure
    4.
    发明公开
    Complementary metal oxide silicon (CMOS) device structure 失效
    Anordnung von CMOS-Typ。

    公开(公告)号：EP0321763A2

    公开(公告)日：1989-06-28

    申请号：EP88120242.8

    申请日：1988-12-05

    申请人： International Business Machines Corporation

    发明人： Kenney, Donald McAlpine

    IPC分类号： H01L23/52 ,  H01L23/528 ,  H01L21/74 ,  H01L21/82

    CPC分类号： H01L27/1104 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A sub-surface interconnection structure for coupling an n-type diffusion (62) to a p-type diffusion (54). The structure is a conductor-filled trench (100) disposed between the diffusion regions. The trench has a thin dielectric layer (110) on its sidewalls and bottom. The conductor (120) within the trench contacts the diffusion regions. Parasitic device formation between the diffusion regions is suppressed because the trench provides a parasitic gate that is shorted to the parasitic source regions (i.e., the coupled diffusion regions). Moreover, the trench provides an enlarged contact to the coupled diffusion regions for the subsequently-applied metal layer.

    摘要翻译： 用于将n型扩散（62）耦合到p型扩散（54）的子表面互连结构。 该结构是设置在扩散区之间的导体填充沟槽（100）。 沟槽在其侧壁和底部具有薄的介电层（110）。 沟槽内的导体（120）与扩散区接触。 由于沟槽提供与寄生源极区域（即耦合扩散区域）短路的寄生栅极，所以抑制了扩散区域之间的寄生器件形成。 此外，沟槽为随后施加的金属层的耦合扩散区提供放大的接触。

    Methods of making high density V-MOS memory arrays
    6.
    发明公开
    Methods of making high density V-MOS memory arrays 失效
    制造高密度V-MOS记忆阵列的方法

    公开(公告)号：EP0044950A3

    公开(公告)日：1983-01-26

    申请号：EP81104920

    申请日：1981-06-25

    申请人： International Business Machines Corporation

    发明人： Kenney, Donald McAlpine

    IPC分类号： H01L21/82 ,  H01L21/90 ,  H01L21/28 ,  H01L21/60

    CPC分类号： H01L27/10876 ,  H01L21/30608 ,  H01L21/76877 ,  H01L27/10823 ,  Y10S438/901

    摘要： 0 A method for providing high density dynamic memory cells which provides self-alignment of both V-MOSFET device elements and their interconnections through the use of a device-defining masking layer (16) having a plurality of parallel thick (16a) and thin regions (16b). Perpendicular strip-like regions (16c) of masking layer (16) are removed to expose square apertures on the surface of substrate (10, 14) in which recesses (18) are formed by an anisotropic etchant. V-MOSFET devices having self- aligned gate electrodes are formed in the recesses (18) and device interconnecting lines are formed under the remaining portions of the thin regions (16b). A combination of anisotropic etching and directionally dependent etching, such as reaction ion etching, may be used to extend the depth of the recesses.