公开(公告)号：EP4020711B1

公开(公告)日：2024-10-09

申请号：EP21195238.7

申请日：2021-09-07

IPC分类号： H01Q15/00 ,  H01Q1/22 ,  H01Q15/14 ,  H01L23/552 ,  H01L23/66 ,  G06F13/14 ,  G06F13/40 ,  H01L23/00 ,  H01L25/03 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L2224/1623520130101 ,  H01L2924/1519220130101 ,  H01L2924/153120130101 ,  H01L2224/1614620130101 ,  H01L2224/1614520130101 ,  H01L2224/1622720130101 ,  H01L2224/1718120130101 ,  H01L2225/0651320130101 ,  H01L2225/0651720130101 ,  H01L2225/0654120130101 ,  H01L2225/0656520130101 ,  H01L25/0652 ,  H01L2225/0653120130101 ,  H01L2223/667720130101 ,  H01L25/10 ,  H01L25/03 ,  H01L2924/1531120130101 ,  H01L23/66 ,  H01Q1/2283 ,  H01L24/16 ,  H01L24/17 ,  H01L2225/104720130101 ,  H01L2924/143420130101 ,  H01L2924/143620130101 ,  H01L2924/143220130101 ,  H01L25/0655 ,  H01L23/552 ,  H01L2924/302520130101 ,  H01Q15/002 ,  H01Q15/148 ,  G06F13/14 ,  G06F13/4068

公开(公告)号：EP4406025A1

公开(公告)日：2024-07-31

申请号：EP22769480.9

申请日：2022-08-23

申请人： QUALCOMM INCORPORATED

发明人： FENG, Chien-Te ,  YIN, Wen ,  SALMON, Jay Scott

IPC分类号： H01L25/16 ,  H01L23/36 ,  H01L23/552 ,  H01L23/00

CPC分类号： H01L25/16 ,  H01L23/552 ,  H01L2224/7325320130101 ,  H01L2924/1532120130101 ,  H01L2924/1816120130101 ,  H01L2224/040120130101 ,  H01L2224/0402620130101 ,  H01L2924/302520130101 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/3677 ,  H01L2224/1622720130101 ,  H01L2224/3224520130101 ,  H01L2224/0556820130101 ,  H01L2224/8381520130101 ,  H01L2224/8181520130101 ,  H01L2224/9222520130101 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/73 ,  H01L24/29 ,  H01L24/13 ,  H01L24/05 ,  H01L23/5383 ,  H01L23/5384

公开(公告)号：EP4401078A1

公开(公告)日：2024-07-17

申请号：EP22871070.3

申请日：2022-11-25

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： LIU, Peng ,  ZHANG, Baohua

IPC分类号： G11C5/04 ,  H01L21/48 ,  H01L23/31 ,  H01L21/58 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10

CPC分类号： G11C5/04 ,  H01L23/49822 ,  H01L23/5383 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/552 ,  H01L25/0657 ,  H01L25/0655 ,  H01L25/105 ,  H01L2225/105820130101 ,  H01L2225/102320130101 ,  H01L2225/103520130101 ,  H01L2225/0654120130101 ,  H01L2225/0654820130101 ,  H01L25/50

摘要： The present disclosure provides a chip package structure, a manufacturing method thereof and an electronic device, and relates to the field of semiconductor technologies, for the purposes of reducing the area of the chip package structure and improving the rate of signal transmission. The semiconductor structure includes a package substrate, a first chip, a conductive pillar and a second chip, wherein the package substrate has a first surface; the first chip is located on the first surface of the package substrate and electrically connected to the package substrate; the conductive pillar is located on the first surface of the package substrate and electrically connected to the package substrate; the second chip is located on a side of the first chip and the conductive pillar away from the package substrate and electrically connected to the conductive pillar; and an orthographic projection of the conductive pillar on the package substrate is located within a range of an orthographic projection of the first chip or the second chip on the package substrate. The chip package structure is configured for connection with a circuit board in the electronic device.

公开(公告)号：EP4388588A1

公开(公告)日：2024-06-26

申请号：EP22765688.1

申请日：2022-08-18

申请人： Raytheon Company

发明人： DEJARLD, Matthew ,  LAROCHE, Jeffrey R. ,  TRULLI, Susan C.

IPC分类号： H01L23/552 ,  H01L27/144

CPC分类号： H01L23/552

公开(公告)号：EP1652234B1

公开(公告)日：2018-12-26

申请号：EP04744703.2

申请日：2004-07-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： WYLAND, Chris

IPC分类号： H01L23/64 ,  H01L23/552 ,  H01L23/367 ,  H01L23/49

CPC分类号： H01L24/73 ,  H01L23/04 ,  H01L23/3672 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/91 ,  H01L2223/6611 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/73221 ,  H01L2224/73229 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/1616 ,  H01L2924/1617 ,  H01L2924/163 ,  H01L2924/166 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A structure provides for the control of bond wire impedance. In an example embodiment, there is an integrated circuit device comprising a semiconductor device die having a plurality of grounding pads, signal pads, and power pads and a package for mounting the integrated circuit and includes a conductive path having at least one reference trace that surrounds the integrated circuit. A grounding arch is disposed over the semiconductor device die.

公开(公告)号：EP2705572B1

公开(公告)日：2018-11-21

申请号：EP12779473.3

申请日：2012-04-27

申请人： Intel Corporation

发明人： KAMGAING, Telesphor

IPC分类号： H01Q21/12 ,  H01Q1/12 ,  H01L23/552 ,  H01Q3/26 ,  H01Q21/06 ,  H01Q1/22 ,  H01L23/00 ,  H01Q21/00

CPC分类号： H01Q1/1271 ,  H01L23/552 ,  H01L24/16 ,  H01L24/17 ,  H01L2223/6677 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1421 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01Q1/2283 ,  H01Q3/26 ,  H01Q21/0087 ,  H01Q21/0093 ,  H01Q21/065 ,  Y10T29/49016 ,  H01L2924/00

摘要： A glass-based, high-performance 60 GHz/mm-wave antenna includes cavities disposed in a phased-array antenna (PAA) substrate. The cavities are disposed below planar antenna elements. Emitter traces are disposed on the PAA substrate opposite the planar antenna elements and the emitter traces, the cavities, and the planar antenna elements are vertically aligned.

公开(公告)号：EP1913633B1

公开(公告)日：2018-11-14

申请号：EP06788428.8

申请日：2006-07-25

申请人： NXP USA, Inc.

发明人： HESS, Kevin J. ,  LEE, Chu-Chung

IPC分类号： H01L23/28 ,  H01L23/367

CPC分类号： H01L23/50 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73207 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package (10) uses a plurality of thermal conductors (56-64) that extend upward within an encapsulant (16) from one or more thermal bond pads (22, 24, 26) on a die (14) to disperse heat. The thermal conductors may be bond wires or conductive stud bumps and do not extend beyond a lateral edge of the die. One or more of the thermal conductors may be looped within the encapsulant and exposed at an upper surface of the encapsulant. In one form a heat spreader (68) is placed overlying the encapsulant for further heat removal. In another form the heat spreader functions as a power or ground terminal directly to points interior to the die via the thermal conductors. Active bond pads may be placed exclusively along the die's periphery or also included within the interior of the die.

公开(公告)号：EP3378293A1

公开(公告)日：2018-09-26

申请号：EP16866833.3

申请日：2016-10-28

申请人： Laird Technologies, Inc.

发明人： WRONA, Timothy M. ,  ENGLISH, Gerald R. ,  JACKLINSKI, Daniel

IPC分类号： H05K9/00 ,  H05K7/20

CPC分类号： H05K9/0081 ,  H01L23/3675 ,  H01L23/4093 ,  H01L23/552 ,  H05K7/2039 ,  H05K7/20918 ,  H05K7/20945 ,  H05K9/0032

摘要： A shielding assembly is disclosed, the assembly including at least a board level shield and a heat sink. The assembly may include a board level shield that includes both a lid and a fence, and may also include a thermal interface material, where the assembly may be mounted on a printed circuit board to provide both EMI shielding and thermal management of heat-generating electronic components or heat sources on the circuit board. The heat sink includes at least one pin, and the shield includes at least one complementary perforation relative to the pin, such that an assembled device of the disclosure provides both EMI shielding and thermal management while permitting the transfer of thermal energy via the heat sink pin through the board level shield perforation.

公开(公告)号：EP3371828A1

公开(公告)日：2018-09-12

申请号：EP15907962.3

申请日：2015-11-05

申请人： Intel Corporation

发明人： CHEAH, Bok Eng ,  KONG, Jackson, Chung Peng ,  OOI, Ping Ping ,  OOI, Kooi Chi ,  PERIAMAN, Shanggar

IPC分类号： H01L25/065 ,  H01L25/07 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1816 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.

公开(公告)号：EP3284103A4

公开(公告)日：2018-08-01

申请号：EP16856029

申请日：2016-10-11

申请人： INVENSAS CORP

发明人： AWUJOOLA ABIOLA ,  SUN ZHUOWEN ,  ZOHNI WAEL ,  PRABHU ASHOK S ,  SUBIDO WILLMAR

IPC分类号： H01L23/552 ,  H01L23/49 ,  H01L23/498 ,  H01L25/03 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L23/552 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/215 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4942 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73227 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05599

摘要： Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.