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    Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits
    3.
    发明公开
    Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits 失效
    集成电路装置和方法用于制造凹陷的隔离结构的用于集成电路。

    公开(公告)号：EP0072966A2

    公开(公告)日：1983-03-02

    申请号：EP82107226.1

    申请日：1982-08-10

    申请人： International Business Machines Corporation

    发明人： Joy, Richard Carleton ,  Kemlage, Bernard Michael ,  Mauer IV, John Lester

    IPC分类号： H01L21/76 ,  H01L21/74

    CPC分类号： H01L21/763 ,  H01L21/743 ,  H01L21/76202

    摘要： An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body (2, 4) having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion (14) at and just below the surface of the integrated circuit and a deep portion (30) which extends through the recessed dielectric portion (14) and extends further into the monocrystalline silicon body (2, 4) than the recessed portion. A highly doped polycrystalline silicon substrate contact (30) is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

    Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits
    4.
    发明公开
    Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits 失效
    用于形成集成电路的凹陷隔离结构的集成电路结构和方法

    公开(公告)号：EP0073370A3

    公开(公告)日：1986-06-11

    申请号：EP82107225

    申请日：1982-08-10

    申请人： International Business Machines Corporation

    发明人： Joy, Richard Carleton ,  Kemlage, Bernard Michael ,  Mauer IV, John Lester

    IPC分类号： H01L21/76 ,  H01L21/74

    CPC分类号： H01L21/76202 ,  H01L21/743 ,  H01L21/763

    摘要： An integrated circuit structure having substrate contacts formed as a part of the isolation structure and method for making the same is described. The integrated circuit structure is composed of a monocrystalline silicon body (2, 4) having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion (22, 24) at and just below the surface of the integrated circuit and a deep portion which extends from the side of the recessed dielectric portion opposite to that portion at the surface of said body into the monocrystalline silicon body. A highly doped polycrystalline silicon substrate contact (20) is located within the deep portion of the pattern of isolation. At certain locations the deep portion of the pattern extends to the surface of the silicon body where interconnection metallurgy can electrically contact the polycrystalline silicon so as to form a substrate contact to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

    摘要翻译： 描述了具有形成为隔离结构的一部分的衬底触点的集成电路结构及其制造方法。 集成电路结构由单体硅体（2,4）构成，单体硅体（2,4）具有围绕体内单晶硅区域的介电隔离图形。 电介质隔离图案包括位于集成电路表面正下方的凹陷电介质部分（22,24），以及从凹陷电介质部分的与所述主体表面处的该部分相反的一侧延伸进入 单晶硅体。 高度掺杂的多晶硅衬底触点（20）位于隔离图案的深部内。 在某些位置，图案的深部延伸到硅本体的表面，在该表面处，互连冶金可以与多晶硅电接触，从而形成到隔离件深部底部的衬底触点，其中触点电连接到 硅体。 多种集成电路器件结构中的任何一种可以被结合在单晶硅区域内。 这些器件包括双极型晶体管，场效应晶体管，电容器，二极管，电阻器等。

    Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits
    5.
    发明公开
    Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits 失效
    集成电路的集成电路结构与形成分离电阻结构的方法

    公开(公告)号：EP0072966A3

    公开(公告)日：1986-06-11

    申请号：EP82107226

    申请日：1982-08-10

    申请人： International Business Machines Corporation

    发明人： Joy, Richard Carleton ,  Kemlage, Bernard Michael ,  Mauer IV, John Lester

    IPC分类号： H01L21/76 ,  H01L21/74

    CPC分类号： H01L21/763 ,  H01L21/743 ,  H01L21/76202

    摘要： An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body (2, 4) having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion (14) at and just below the surface of the integrated circuit and a deep portion (30) which extends through the recessed dielectric portion (14) and extends further into the monocrystalline silicon body (2, 4) than the recessed portion. A highly doped polycrystalline silicon substrate contact (30) is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

    Fabrication process for a shallow emitter, narrow intrinsic base transistor
    8.
    发明公开
    Fabrication process for a shallow emitter, narrow intrinsic base transistor 失效
    微型发光二极管内部基极晶体管的制造工艺

    公开(公告)号：EP0094482A3

    公开(公告)日：1986-10-08

    申请号：EP83102360

    申请日：1983-03-10

    申请人： International Business Machines Corporation

    发明人： Kemlage, Bernard Michael

    IPC分类号： H01L21/225 ,  H01L29/08 ,  H01L29/10 ,  H01L29/72

    CPC分类号： H01L29/1004 ,  H01L21/033 ,  H01L21/2257 ,  H01L29/7325 ,  Y10S438/92 ,  Y10S438/965

    摘要： A high performance bipolar transistor having a shallow emitter and a narrow intrinsic base region is fabricated by a minimum number of process steps. A silicon semiconductor body 10 is provided with regions of monocrystalline silicon isolated from one another by isolation regions (18) an epitaxial layer (14) and a buried subcollector (12). A layer (24) of polycrystalline silicon is deposited on the body. The surface of the polycrystalline silicon layer (24) is oxidized and the polycrystalline silicon is implanted with a base impurity. Silicon nitride and oxide layers (28, 30) are deposited on the polysilicon layer. An opening is made in the surface oxide layer (28) and the silicon nitride layer (30) to define the emitter area of the transistor. The polycrystalline silicon is thermally oxidized to drive the base impurity into the substrate. The thermal oxide is removed in an isotropic etch to leave an oxide sidewall cover (38) on the polycrystalline silicon. An emitter impurity is ion implanted into the polycrystalline silicon in the emitter area and then driven into the substrate. Collector, base and emitter contact openings are made and conductive metallurgy is formed.

    Method of forming emitter and intrinsic base regions of a bipolar transistor
    9.
    发明公开
    Method of forming emitter and intrinsic base regions of a bipolar transistor 失效
    一种用于制造双极晶体管的发射极和本征基极区域的方法。

    公开(公告)号：EP0090940A2

    公开(公告)日：1983-10-12

    申请号：EP83101761.1

    申请日：1983-02-23

    申请人： International Business Machines Corporation

    发明人： Barson, Fred ,  Kemlage, Bernard Michael

    IPC分类号： H01L21/225 ,  H01L21/285 ,  H01L21/82 ,  H01L29/10

    CPC分类号： H01L29/66272 ,  H01L21/2257 ,  H01L21/32155 ,  H01L29/1004 ,  H01L29/66287

    摘要： A method for fabricating high performance NPN bipolar transistors which result in shallow, narrow base devices is described.
    The method includes depositing a polycrystalline silicon layer (30) over a monocrystalline silicon surface in which the base and emitter regions (42, 44) of the transistor are to be formed. Boron ions (32) are ion implanted into the polycrystalline silicon layer (30) near the interface of the polycrystalline silicon layer with the monocrystalline silicon layer. An annealing of the layer structure partially drives in the boron into the monocrystalline silicon substrate. Arsenic ions (38) are ion implanted into the polycrystalline silicon layer (30). A second annealing step is utilized to fully drive in the boron to form the base region (42) and simultaneously therewith drive in the arsenic to form the emitter region (44) of the transistor. This process involving a two-step annealing process for the boron implanting ions is necessary to create a base with sufficient width and doping to avoid punch-through. There is also described a method for forming NPN transistors in an integrated circuit.