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公开(公告)号：EP0175080B1
公开(公告)日：1991-11-13
申请号：EP85108699.1
申请日：1985-07-12
IPC分类号： G06F12/08
CPC分类号： G06F12/0893
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公开(公告)号：EP0175080A2
公开(公告)日：1986-03-26
申请号：EP85108699.1
申请日：1985-07-12
IPC分类号： G06F12/08
CPC分类号： G06F12/0893
摘要： @ A microcomputer memory system is organized into a plurality of banks (12). Each bank consists of an array of static column mode dynamic random access memories (DRAMs) of the type having an on-chip static buffer for storing an entire row. The static buffers associated with each bank functions as a distributed cache (24) to hold the last accessed row for the associated bank. A memory controller (18) receives real addresses from CPU (10) or other device on the memory bus (14) and extracts bank and row numbers from the address. The memory controller determines whether the accessed row for a memory bank is in the distributed cache and, if it is, accesses the distributed cache for that bank. Otherwise, the memory controller switches the contents of the distributed cache with the contents of the addressed row for that bank.
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公开(公告)号：EP0218794B1
公开(公告)日：1990-10-17
申请号：EP86108504.1
申请日：1986-06-21
发明人： Kirkpatrick, Edward Scott , Kronstadt, Eric Paul , Montoye, Robert Kevin , Wilcke, Winfried Wolfgang
CPC分类号： G06F11/2215 , G01R31/318541 , G01R31/318572 , G01R31/31858 , G06F11/0751
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公开(公告)号：EP0175080A3
公开(公告)日：1988-07-27
申请号：EP85108699
申请日：1985-07-12
IPC分类号： G06F12/08
CPC分类号： G06F12/0893
摘要： @ A microcomputer memory system is organized into a plurality of banks (12). Each bank consists of an array of static column mode dynamic random access memories (DRAMs) of the type having an on-chip static buffer for storing an entire row. The static buffers associated with each bank functions as a distributed cache (24) to hold the last accessed row for the associated bank. A memory controller (18) receives real addresses from CPU (10) or other device on the memory bus (14) and extracts bank and row numbers from the address. The memory controller determines whether the accessed row for a memory bank is in the distributed cache and, if it is, accesses the distributed cache for that bank. Otherwise, the memory controller switches the contents of the distributed cache with the contents of the addressed row for that bank.
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5.发明公开A method and apparatus for improving performance of out of sequence load operations in a computer system 失效方法以及用于在计算机系统中的非连续的加载操作的功率增加设备。
公开(公告)号：EP0568842A2
公开(公告)日：1993-11-10
申请号：EP93106058.6
申请日：1993-04-14
CPC分类号： G06F8/445 , G06F9/3834
摘要： The invention provides for improved performance of out of sequence load operations to increase the overall data processing speed of a computer. The system has an improved compiler, with an optimizer, an improved CPU with four new instructions in its instruction set, and an address compare unit (ACU). During program compilation, the improved compiler identifies load operations that can be move out of sequence ahead of associated store operations and moves those load operations out of sequence and flags them as such. The associated store operations are also flagged. During processor execution of a compiled and optimized program, the address of operands fetched by the out of sequence load operations are saved to the new associative memory. On request, the ACU compares the addresses saved to the addresses generated by the associated store operations. If a comparison results in an identity between the address of a store operation and an address of the out of sequence load operation, a recovery code is run to correct the problem. If there is no match between the addresses, the system continues to execute the program in its compiled order. The system clears addresses saved in the ACU when it is no longer necessary to compare those addresses to the addresses generated by store operations. The system also has the ability to work in a multiprogramming or multitasking environment.
摘要翻译： 本发明提供了改进的失序负载操作的性能提高的计算机的整体的数据处理速度。 该系统具有改进的编译器，优化器与，改善与它的指令集四个新的指令，CPU和处理比较单元（ACU）。 在程序编译，改进编译标识加载操作确实可以提前关联的存储操作的搬出顺序和移动这些负荷运行失序，并将其标记为此类。 因此，相关的存储操作标记。 期间编译和优化程序的处理器执行时，通过乱序加载操作的取出操作数的地址，并保存到新的关联存储器。 根据要求，ACU保存比较受与之相关的存储操作生成的地址的地址。 如果在商店业务和给出序列负载操作的地址的地址之间的身份的比较结果，恢复代码运行以纠正的麻烦。 如果在地址之间不匹配，系统将继续在其编译为执行程序。 该系统清除保存在ACU地址当它不再需要这些地址进行比较的存储操作生成的地址。 因此，该系统具有多道或多任务环境中工作的能力。
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公开(公告)号：EP0179245A2
公开(公告)日：1986-04-30
申请号：EP85111332.4
申请日：1985-09-07
IPC分类号： G06F9/38
CPC分类号： G06F9/3806
摘要： @ A branch target table (10) is used as an instruction memory which is referenced by the addresses of instructions which are targets of branches. The branch target table consists of a target address table (12), a next fetch address table (14), a valid entries table (16) and an instruction table (18). Whenever a branch is taken, some of the bits in the untranslated part of the address of the target instruction, i.e. the instruction being branched to, are used to address a line of the branch target table (10). In parallel with address translation, all entries of the branch target table line are accessed, and the translated address is compared to the target address table (12) entry on that line. If the target address table entry matches the target address, the instruction prefetch unit (32) fetches the instruction addressed by the next fetch address table (14) entry for the given line and the line of instructions associated with the branch address table entry is read into an instruction queue (38) having a length set by the valid entry table (16) entry which indicates how many of these instructions are valid. Otherwise, the instruction prefetch unit (32) fetches the target and subsequent instructions as it would if there were no branch target table, and the target address table entry is set to the real address of the target instruction. The next fetch address table (14) is updated so that it always contains the address of the instruction which follows the last valid instruction in the line, and the valid entries table (16) is updated so that it always counts the number of valid instructions in the line.
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7.发明公开A method and apparatus for improving performance of out of sequence load operations in a computer system 失效一种用于改善计算机系统中的失序负载操作的性能的方法和装置
公开(公告)号：EP0568842A3
公开(公告)日：1994-01-05
申请号：EP93106058.6
申请日：1993-04-14
CPC分类号： G06F8/445 , G06F9/3834
摘要： The invention provides for improved performance of out of sequence load operations to increase the overall data processing speed of a computer. The system has an improved compiler, with an optimizer, an improved CPU with four new instructions in its instruction set, and an address compare unit (ACU). During program compilation, the improved compiler identifies load operations that can be move out of sequence ahead of associated store operations and moves those load operations out of sequence and flags them as such. The associated store operations are also flagged. During processor execution of a compiled and optimized program, the address of operands fetched by the out of sequence load operations are saved to the new associative memory. On request, the ACU compares the addresses saved to the addresses generated by the associated store operations. If a comparison results in an identity between the address of a store operation and an address of the out of sequence load operation, a recovery code is run to correct the problem. If there is no match between the addresses, the system continues to execute the program in its compiled order. The system clears addresses saved in the ACU when it is no longer necessary to compare those addresses to the addresses generated by store operations. The system also has the ability to work in a multiprogramming or multitasking environment.
摘要翻译： 本发明提供了改进的失序负载操作的性能，以提高计算机的总体数据处理速度。 该系统具有改进的编译器，带有优化器，改进的CPU，其指令集中包含四条新指令，以及一个地址比较单元（ACU）。 在程序编译期间，改进的编译器会识别在相关存储操作之前移出序列的加载操作，并将这些加载操作移出序列并将其标记为这样。 关联的商店操作也被标记。 在编译和优化程序的处理器执行期间，由不按顺序加载操作获取的操作数的地址被保存到新的关联存储器中。 根据请求，ACU将保存的地址与相关存储操作生成的地址进行比较。 如果比较导致存储操作的地址与无序序列加载操作的地址之间存在同一性，则会运行恢复代码以纠正该问题。 如果地址之间没有匹配，则系统继续按编译顺序执行程序。 当不再需要将这些地址与存储操作生成的地址进行比较时，系统会清除保存在ACU中的地址。 该系统还能够在多程序或多任务环境中工作。
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公开(公告)号：EP0179245B1
公开(公告)日：1991-05-08
申请号：EP85111332.4
申请日：1985-09-07
IPC分类号： G06F9/38
CPC分类号： G06F9/3806
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公开(公告)号：EP0179245A3
公开(公告)日：1988-04-20
申请号：EP85111332
申请日：1985-09-07
IPC分类号： G06F09/38
CPC分类号： G06F9/3806
摘要： @ A branch target table (10) is used as an instruction memory which is referenced by the addresses of instructions which are targets of branches. The branch target table consists of a target address table (12), a next fetch address table (14), a valid entries table (16) and an instruction table (18). Whenever a branch is taken, some of the bits in the untranslated part of the address of the target instruction, i.e. the instruction being branched to, are used to address a line of the branch target table (10). In parallel with address translation, all entries of the branch target table line are accessed, and the translated address is compared to the target address table (12) entry on that line. If the target address table entry matches the target address, the instruction prefetch unit (32) fetches the instruction addressed by the next fetch address table (14) entry for the given line and the line of instructions associated with the branch address table entry is read into an instruction queue (38) having a length set by the valid entry table (16) entry which indicates how many of these instructions are valid. Otherwise, the instruction prefetch unit (32) fetches the target and subsequent instructions as it would if there were no branch target table, and the target address table entry is set to the real address of the target instruction. The next fetch address table (14) is updated so that it always contains the address of the instruction which follows the last valid instruction in the line, and the valid entries table (16) is updated so that it always counts the number of valid instructions in the line.
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公开(公告)号：EP0218794A1
公开(公告)日：1987-04-22
申请号：EP86108504.1
申请日：1986-06-21
发明人： Kirkpatrick, Edward Scott , Kronstadt, Eric Paul , Montoye, Robert Kevin , Wilcke, Winfried Wolfgang
CPC分类号： G06F11/2215 , G01R31/318541 , G01R31/318572 , G01R31/31858 , G06F11/0751
摘要： An improved testing and checking circuit for a Differential Cascode Voltage Switch which uses N-devices for both the invalid (0.0) and (1.1) state detection of Q and Q switch signals, and uses decoupling pass devices for sampling the data at the fall of the system C-clock, additionally allowing simultaneous pre-charging and error detection. The testing and checking circuit is incorporated in a hierarchical scheme, which uses the system C-clock for input to the latches, decoupling of the buffers, and pulling up and down the error lines. The error fault is held in a system latch. Also described is a circuit scheme which self tests a large macro using only the C-clock and latches the result in a single latch. More particularly, the described circuit employs the Q and Q signals in a NOR configuration circuit 30, 32, 34, thus detecting if neither signal has sufficient voltage to pull down the load device 34 which consists of a P-device whose gate is attached to the C-clock. The resulting signal is run to a gate 44 in parallel with the two N-devices 44, 46. Thus, the two low signals allow this NOR gate to rise and produce a pulldown leg to an error line 24. An invalid signal condition is detected if either both signals are sufficiently high to turn on an N-device or neither signal is high enough to turn on N-devices 46, 48. Therefore, the described circuit registers a failure if and only if there is the potential for a tree with the same inputs to enter an invalid state.
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