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1.发明公开Highly integrated universal tape bonding of semiconductor chips 失效Hochintegrierte universelle Streifenverbindung vonHalbleiterplättchen。
公开(公告)号：EP0130498A1
公开(公告)日：1985-01-09
申请号：EP84107153.3
申请日：1984-06-22
IPC分类号： H05K13/00
CPC分类号： H01L24/86 , H01L21/67144 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/00
摘要： A method of forming semiconductor devices wherein a continuous metallic sheet (14) is cut (16, 18) under computer (10) control into a personalized lead pattern. The pattern is then moved to a bonding station (40). A bonding tool (32) actuated by computer control moves from one terminal end to another to sequentially bond terminals to the semiconductor device (26). A variety of various patterns and chips can be handled on the same line using common cutting and bonding tools. A second bond can be made from the lead pattern to either a lead frame (30) or a substrate (50).
摘要翻译： 一种形成半导体器件的方法，其中将连续金属片（14）在计算机（10）下被切割（16,18）控制成个性化引线图案。 然后将图案移动到粘合台（40）。 通过计算机控制致动的接合工具（32）从一个终端移动到另一端，以将端子顺序地接合到半导体器件（26）。 各种图案和芯片可以在同一条线上使用常用的切割和粘合工具进行处理。 可以从引线图案到引线框架（30）或基板（50）形成第二接合。
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2.发明公开
公开(公告)号：EP0186818A2
公开(公告)日：1986-07-09
申请号：EP85115710.7
申请日：1985-12-10
IPC分类号： H01L23/48
CPC分类号： H01L24/81 , H01L23/49861 , H01L2224/16 , H01L2224/81801 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01061 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14
摘要： A self aligning integrated circuit package including a flexible insulated lead frame (11) and a flip chip (16) having a plurality of input/output solder balls (17) in predetermined positions thereon. The lead frame is provided with a plurality of flexible metallic leads (13) on an insulation coating. A plurality of openings is etched in the insulating coating over the ends of the leads to be connected to the solder balls on the chip. These openings in the insulation are in the same pattern as the balls on the chip and act as a jig to assure that the chip is properly positioned on the lead frame and that the solder balls are contained in a restricted area and provide significant electrical contact to the exposed lead frames.
摘要翻译： 一种自对准集成电路封装，包括在其上的预定位置具有多个输入/输出焊球（17）的柔性绝缘引线框架（11）和倒装芯片（16）。 引线框架在绝缘涂层上设置有多个柔性金属引线（13）。 在引线的端部上的绝缘涂层中蚀刻多个开口以连接到芯片上的焊球。 绝缘体中的这些开口具有与芯片上的球相同的图案，并且用作夹具以确保芯片适当地定位在引线框架上，并且焊球被容纳在限制区域中并提供显着的电接触 暴露的引线框架。
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公开(公告)号：EP0186818A3
公开(公告)日：1987-03-18
申请号：EP85115710
申请日：1985-12-10
IPC分类号： H01L23/48
CPC分类号： H01L24/81 , H01L23/49861 , H01L2224/16 , H01L2224/81801 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01061 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14
摘要： A self aligning integrated circuit package including a flexible insulated lead frame (11) and a flip chip (16) having a plurality of input/output solder balls (17) in predetermined positions thereon. The lead frame is provided with a plurality of flexible metallic leads (13) on an insulation coating. A plurality of openings is etched in the insulating coating over the ends of the leads to be connected to the solder balls on the chip. These openings in the insulation are in the same pattern as the balls on the chip and act as a jig to assure that the chip is properly positioned on the lead frame and that the solder balls are contained in a restricted area and provide significant electrical contact to the exposed lead frames.
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公开(公告)号：EP0186818B1
公开(公告)日：1991-03-06
申请号：EP85115710.7
申请日：1985-12-10
IPC分类号： H01L23/48
CPC分类号： H01L24/81 , H01L23/49861 , H01L2224/16 , H01L2224/81801 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01061 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14
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公开(公告)号：EP0081135B1
公开(公告)日：1987-03-18
申请号：EP82110816.4
申请日：1982-11-23
CPC分类号： H01L24/85 , H01L23/538 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/91 , H01L2224/16225 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48229 , H01L2224/4823 , H01L2224/48491 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48699 , H01L2224/48724 , H01L2224/48744 , H01L2224/49175 , H01L2224/73257 , H01L2224/73265 , H01L2224/85051 , H01L2224/85205 , H01L2224/85424 , H01L2224/85444 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15312 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H05K3/4015 , H01L2924/00014 , H01L2224/78 , H01L2924/00
摘要： A novel substrate is disclosed which can mount either flip-chip solder bonded IC chips or wire bonded chips, or both chips, or a single chip having both solder bonds and wire bonds is disclosed. The substrate has an array of solder pads which will accept solder bonds. Those pads which are to be used for wire bonding have mounted thereon a trimetallic pedestal. Each pedestal has a layer of solder metal bonded to the solder pad, a top layer metal suitable for wire bonding, such as, aluminum or gold, and an intermediate layer of metal, such as nickel, which is impervious to both solder metal and the top layer metal.
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公开(公告)号：EP0130498B1
公开(公告)日：1987-09-23
申请号：EP84107153.3
申请日：1984-06-22
IPC分类号： H05K13/00
CPC分类号： H01L24/86 , H01L21/67144 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/00
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公开(公告)号：EP0081135A3
公开(公告)日：1984-07-25
申请号：EP82110816
申请日：1982-11-23
CPC分类号： H01L24/85 , H01L23/538 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/91 , H01L2224/16225 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48229 , H01L2224/4823 , H01L2224/48491 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48699 , H01L2224/48724 , H01L2224/48744 , H01L2224/49175 , H01L2224/73257 , H01L2224/73265 , H01L2224/85051 , H01L2224/85205 , H01L2224/85424 , H01L2224/85444 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15312 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H05K3/4015 , H01L2924/00014 , H01L2224/78 , H01L2924/00
摘要： A novel substrate (10) is disclosed which can mount either flip-chip solder bonded IC chips (12) or wire bonded chips (18), or both chips, or a single chip having both solder bonds and wire bond. The substrate has an array of solder pads (26,28) which will accept solder bonds. Those pads (28) which are to be used for wire bonding have mounted thereon a trimetallic pedestal (30). Each pedestal has a layer (32) of solder metal bonded to the solder pad, a top layer metal (34) suitable for wire bonding, such as, aluminum or gold, and an intermediate layer (36) of metal, such as nickel, which is impervious to both solder metal and the top layer metal.
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公开(公告)号：EP0081135A2
公开(公告)日：1983-06-15
申请号：EP82110816.4
申请日：1982-11-23
CPC分类号： H01L24/85 , H01L23/538 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/91 , H01L2224/16225 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48229 , H01L2224/4823 , H01L2224/48491 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48699 , H01L2224/48724 , H01L2224/48744 , H01L2224/49175 , H01L2224/73257 , H01L2224/73265 , H01L2224/85051 , H01L2224/85205 , H01L2224/85424 , H01L2224/85444 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15312 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H05K3/4015 , H01L2924/00014 , H01L2224/78 , H01L2924/00
摘要： A novel substrate (10) is disclosed which can mount either flip-chip solder bonded IC chips (12) or wire bonded chips (18), or both chips, or a single chip having both solder bonds and wire bond. The substrate has an array of solder pads (26,28) which will accept solder bonds. Those pads (28) which are to be used for wire bonding have mounted thereon a trimetallic pedestal (30). Each pedestal has a layer (32) of solder metal bonded to the solder pad, a top layer metal (34) suitable for wire bonding, such as, aluminum or gold, and an intermediate layer (36) of metal, such as nickel, which is impervious to both solder metal and the top layer metal.
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