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    Bipolar transistor
    3.
    发明公开
    Bipolar transistor 审中-公开
    Bipolartransistor

    公开(公告)号：EP2996153A1

    公开(公告)日：2016-03-16

    申请号：EP14184549.5

    申请日：2014-09-12

    申请人： NXP B.V.

    发明人： Vanhoucke, Tony ,  Dinh, Viet Thanh ,  Magnee, Petrus Hubertus Cornelis ,  Ponky, Ivo ,  Klaassen, Dirk ,  Al-Sa'di, Mahmoud Shehab Mohammad

    IPC分类号： H01L29/737 ,  H01L21/331 ,  H01L29/06 ,  H01L29/36 ,  H01L29/08

    CPC分类号： H01L29/063 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/36 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7378 ,  H03F3/21

    摘要： A bipolar transistor includes a collector including a laterally extending drift region. The bipolar transistor also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a doped region having a conductivity type that is different to that of the collector. The doped region extends laterally beneath the collector to form a junction at a region of contact between the doped region and the collector. The doped region has a non-uniform lateral doping profile. A doping level of the doped region is highest in a part of the doped region closest to a collector-base junction of the bipolar transistor.

    摘要翻译： 双极晶体管包括具有横向延伸漂移区的集电极。 双极晶体管还包括位于集电极上方的基极。 双极晶体管还包括位于基极上方的发射极。 双极晶体管还包括具有不同于集电极的导电类型的掺杂区域。 掺杂区域在集电极之下横向延伸以在掺杂区域和集电极之间的接触区域处形成结。 掺杂区域具有非均匀的横向掺杂分布。 在最接近双极晶体管的集电极 - 基极结的掺杂区域的一部分中，掺杂区域的掺杂水平最高。

    METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR
    6.
    发明授权
    METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR 有权
    用于生产双极晶体管

    公开(公告)号：EP2062291B1

    公开(公告)日：2011-11-02

    申请号：EP07826193.0

    申请日：2007-08-29

    申请人： NXP B.V.

    发明人： DONKERS, Johannes, J., T., M. ,  NUTTINCK, Sebastien ,  BOCCARDI, Guillaume L., R. ,  NEUILLY, Francois

    IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L29/40

    CPC分类号： H01L29/7378 ,  H01L29/407 ,  H01L29/66242

    摘要： The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7). A second base layer (13) is formed on the isolation layer (10), thereby forming the field plate (17), on the top surface of the collector region (21), thereby forming a base region (31), and on a sidewall of the first base layer (4), thereby forming an electrical connection between the first base layer (4), the base region (31) and the field plate (17). An emitter region (41) is formed on a top part of the base region (31), thereby forming the Resurf bipolar transistor.

    Spacer formation in the fabrication of planar bipolar transistors
    7.
    发明公开
    Spacer formation in the fabrication of planar bipolar transistors 有权
    Abstshalterstruktur bei der Herstellung von flachen Bipolartransistoren

    公开(公告)号：EP2372754A1

    公开(公告)日：2011-10-05

    申请号：EP10250714.2

    申请日：2010-04-01

    申请人： NXP B.V.

    发明人： Donkers, Johannes Josephus Theodorus Marinus ,  VanHoucke, Tony ,  Mertens, Hans ,  Meunier-Beillard, Philippe

    IPC分类号： H01L21/331 ,  H01L29/08

    CPC分类号： H01L29/66318 ,  H01L29/0817 ,  H01L29/66242

    摘要： A bipolar transistor is fabricated having a collector (52) in a substrate (1) and a base (57, 58) and an emitter (59) formed over the substrate. The base has a stack region (57) which is laterally separated from the emitter (59) by an electrically insulating spacer (71). The insulating spacer (71) has a width dimension at its top end at least as large as the width dimension at its bottom end and forms a r-shape or an oblique shape. The profile reduces the risk of silicide bridging at the top of the spacer in subsequent processing, while maintaining the width of emitter window.

    摘要翻译： 制造了在衬底（1）中具有集电极（52）和形成在衬底上的基极（57,58）和发射极（59）的双极晶体管。 底座具有通过电绝缘间隔件（71）与发射器（59）横向分开的堆叠区域（57）。 绝缘间隔物（71）在其顶端的宽度尺寸至少与其底端的宽度尺寸一样大，形成r形或倾斜形状。 该轮廓降低了后续处理中间隔物顶部的硅化物桥接的风险，同时保持了发射器窗口的宽度。

    METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR AND BIPOLAR TRANSITOR OBTAINED THEREWITH
    8.
    发明授权
    METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR AND BIPOLAR TRANSITOR OBTAINED THEREWITH 有权
    用于生产双极晶体管和在由双极型晶体管这一过程

    公开(公告)号：EP2038918B1

    公开(公告)日：2011-09-21

    申请号：EP07766732.7

    申请日：2007-06-12

    申请人： NXP B.V.

    发明人： HIJZEN, Erwin ,  MEUNIER-BEILLARD, Philippe ,  DONKERS, Johannes, J., T., M.

    IPC分类号： H01L21/331

    CPC分类号： H01L29/66287 ,  H01L29/66242

    摘要： The invention relates to a method of manufacturing a semiconductor device (10) comprising a substrate (12) and a silicon semiconductor body (11) and comprising a bipolar transistor with an emitter region (1) of a first conductivity type, a base region (2) of a second conductivity type opposite to the first conductivity type, and a collector region (3) of the first conductivity type, on the surface of the semiconductor body (11) in which the collector region (3) is formed at least an epitaxial semiconductor layer (20,21,22) being deposited in which the base region (2) is formed, on top of this an etch stop layer (15) being deposited on which a silicon low-crystalline semiconductor layer (24) is deposited in which a connection zone of the base region (2) is formed and in which at the location of an emitter region (1) to be formed an opening (7) is provided running up to the etch stop layer (15), a portion of the etch stop layer (15) covering the opening (7) being removed by means of etching and also an adjoining portion of the etch stop layer (15), a hollow being created underneath the silicon low-crystalline semiconductor layer (24) adjoining and connected the opening (7), whereinafter a high-crystalline semiconductor layer (5) is formed within the hollow. In a method according to the invention the formation of the high-crystalline semiconductor layer (5) is carried out in such a way that a part of the surface of the semiconductor body (11) adjoining the opening (7) is kept free from the high-crystalline semiconductor layer (5). In this way a high-quality device (10) is obtained in easy manner. The relevant surface is kept free using a cover layer (6) or in a preferred manner even without the use of such a layer.

    Method for manufacturing a junction
    10.
    发明公开
    Method for manufacturing a junction 有权
    HerstellungsverfahrenfüreinenÜbergang

    公开(公告)号：EP2202784A2

    公开(公告)日：2010-06-30

    申请号：EP09180038.3

    申请日：2009-12-18

    申请人： IMEC

    发明人： Nguyen, Ngoc Duy ,  Loo, Roger ,  Caymax, Matty

    IPC分类号： H01L21/205 ,  H01L21/02

    CPC分类号： H01L21/02532 ,  H01L21/02573 ,  H01L29/165 ,  H01L29/66242

    摘要： The present invention relates to a method for manufacturing a junction with a controlled dopant (concentration) profile comprising (or consisting of) the steps of:
    - forming a first semiconductor material comprising a first dopant having a first concentration and thereupon
    - forming a second semiconductor material comprising a second dopant, having a second concentration thereby forming a junction, and
    - depositing by Atomic Layer Epitaxy or Vapor Phase Doping at least a fraction of a monolayer of a precursor suitable to form the second dopant on the first semiconductor material, prior to forming the second semiconductor material, thereby increasing the second concentration of the second dopant at the junction.

    摘要翻译： 本发明涉及一种用于制造具有受控掺杂剂（浓度）分布的结点的方法，包括（或由其组成）以下步骤： - 形成第一半导体材料，该第一半导体材料包括具有第一浓度的第一掺杂剂，并且随后形成第二半导体 具有第二掺杂物的材料，从而形成结，以及 - 通过原子层外延或蒸气相掺杂至少一部分适合于在第一半导体材料上形成第二掺杂剂的前体单层的单层，在 形成第二半导体材料，从而增加第二掺杂剂在该结处的第二浓度。