公开(公告)号：EP2022090B1

公开(公告)日：2014-10-08

申请号：EP07728532.8

申请日：2007-04-25

Applicant: International Business Machines Corporation

Inventor： JAFFE, Mark David ,  DALTON, Timothy Joseph ,  GAMBINO, Jeffrey Peter ,  KARTSCHOKE, Paul David ,  STAMPER, Anthony Kendall c/o IBM United Kingdom Limited Intellectual Property Law ,  BERNSTEIN, Kerry

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

公开(公告)号：EP2095418B1

公开(公告)日：2010-12-01

申请号：EP07822110.8

申请日：2007-10-31

Applicant: International Business Machines Corporation

Inventor： DAUBENSPECK, Timothy Harrison ,  MUZZY, Christopher David ,  GAMBINO, Jeffrey Peter ,  SAUTER, Wolfgang

IPC: H01L23/31 ,  H01L23/485

CPC classification number: H01L23/3171 ,  B23K1/0016 ,  B23K1/20 ,  B23K20/004 ,  B23K2201/40 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/85011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00

Abstract: Methods of forming wire and solder bonds (190, 180) are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond, both regions covered by a silicon nitride layer over a silicon oxide layer (108); forming in a material (130) a first opening to the silicon oxide layer (108) over the wire bond metal region and a second opening exposing the solder bond metal region; forming the solder bond (180) to the solder bond metal region while the wire bond metal region is covered; exposing the wire bond metal region including removing the silicon oxide layer (108) to the wire bond metal region; and forming the wire bond (190) to the wire bond metal region. Wire bonds and solder bonds can be made accessible on a single multi-part wafer (MPW) or on a single chip, if necessary, and can be formed substantially simultaneously.

公开(公告)号：EP2095418A1

公开(公告)日：2009-09-02

申请号：EP07822110.8

申请日：2007-10-31

Applicant: International Business Machines Corporation

Inventor： DAUBENSPECK, Timothy Harrison ,  MUZZY, Christopher David ,  GAMBINO, Jeffrey Peter ,  SAUTER, Wolfgang

IPC: H01L23/31 ,  H01L23/485

CPC classification number: H01L23/3171 ,  B23K1/0016 ,  B23K1/20 ,  B23K20/004 ,  B23K2201/40 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/85011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00

Abstract: Methods of forming wire and solder bonds (190, 180) are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond, both regions covered by a silicon nitride layer over a silicon oxide layer (108); forming in a material (130) a first opening to the silicon oxide layer (108) over the wire bond metal region and a second opening exposing the solder bond metal region; forming the solder bond (180) to the solder bond metal region while the wire bond metal region is covered; exposing the wire bond metal region including removing the silicon oxide layer (108) to the wire bond metal region; and forming the wire bond (190) to the wire bond metal region. Wire bonds and solder bonds can be made accessible on a single multi-part wafer (MPW) or on a single chip, if necessary, and can be formed substantially simultaneously.

Abstract translation: 公开了形成导线和焊料结合（190,180）的方法。 在一个实施例中，一种方法包括提供包括用于引线键合的引线键合金属区域和用于焊料键合的焊料键合金属区域的结构，这两个区域被氧化硅层（108）上方的氮化硅层覆盖; 在材料（130）中形成第一开口，所述第一开口通向所述引线接合金属区域上的所述氧化硅层（108），以及暴露所述焊料接合金属区域的第二开口; 在焊线金属区被覆盖的同时形成焊料结合（180）到焊料结合金属区; 暴露包括去除氧化硅层（108）的引线键合金属区域到引线键合金属区域; 以及将丝焊（190）形成到丝焊金属区域。 如果需要，可以在单个多部分晶圆（MPW）或单个芯片上接入引线键合和焊接键合，并且可以基本同时形成。

公开(公告)号：EP2097202B1

公开(公告)日：2011-02-02

申请号：EP07822113.2

申请日：2007-10-31

Applicant: International Business Machines Corporation

Inventor： DAUBENSPECK, Timothy Harrison ,  SAUTER, Wolfgang ,  GAMBINO, Jeffrey Peter ,  MUZZY, Christopher David

IPC: B23K1/20 ,  B23K20/24 ,  H01L25/065

CPC classification number: B23K1/20 ,  B23K1/0016 ,  B23K20/004 ,  B23K20/24 ,  B23K2201/40 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05548 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/85011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Methods of forming wire and solder bond structures are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region. Wire bond and solder bond structures can be made accessible on a single multi-part wafer (MPW) wafer or on a single chip, if necessary.

公开(公告)号：EP2097202A1

公开(公告)日：2009-09-09

申请号：EP07822113.2

申请日：2007-10-31

Applicant: International Business Machines Corporation

Inventor： DAUBENSPECK, Timothy Harrison ,  SAUTER, Wolfgang ,  GAMBINO, Jeffrey Peter ,  MUZZY, Christopher David

IPC: B23K1/20 ,  B23K20/24 ,  H01L25/065

CPC classification number: B23K1/20 ,  B23K1/0016 ,  B23K20/004 ,  B23K20/24 ,  B23K2201/40 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05548 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/85011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Methods of forming wire and solder bond structures are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region. Wire bond and solder bond structures can be made accessible on a single multi-part wafer (MPW) wafer or on a single chip, if necessary.

Abstract translation: 公开了形成导线和焊接结构的方法。 在一个实施例中，一种方法包括提供包括用于引线键合的引线键合金属区域和用于焊料键合的焊料键合金属区域的结构; 仅在丝焊金属区域上形成保护层; 在所述引线键合金属区域和所述焊料键合金属区域之上的氧化硅层上方形成氮化硅层; 在保持焊线金属区域覆盖的同时形成焊料结合到焊料结合金属区域; 暴露所述丝焊金属区域，包括去除所述保护层; 以及形成到丝焊金属区域的丝焊。 如果需要，可以在单个多部分晶圆（MPW）晶圆或单个芯片上实现引线键合和焊接键合结构。

公开(公告)号：EP2022090A1

公开(公告)日：2009-02-11

申请号：EP07728532.8

申请日：2007-04-25

Applicant: International Business Machines Corporation

Inventor： JAFFE, Mark David ,  DALTON, Timothy Joseph ,  GAMBINO, Jeffrey Peter ,  KARTSCHOKE, Paul David ,  STAMPER, Anthony Kendall ,  BERNSTEIN, Kerry

IPC: H01L21/768 ,  H01L27/12

CPC classification number: H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.