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公开(公告)号：EP1384354B8
公开(公告)日：2012-09-05
申请号：EP02719909.0
申请日：2002-01-31
发明人： CALVIGNAC, Jean, Louis , GOETZINGER, William, John , HANDLOGTEN, Glen, Howard , HEDDES, Marco, C. , LOGAN, Joseph, Franklin , MIKOS, James, Francis , NORGAARD, David, Alan , VERPLANKEN, Fabrice
CPC分类号： H04L12/5601 , H04L2012/5636 , H04L2012/5679 , H04L2012/5685
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公开(公告)号：EP1864463B1
公开(公告)日：2009-07-15
申请号：EP06708769.2
申请日：2006-03-15
发明人： BASSO, Claude , CALVIGNAC, Jean , CHANG, Chih-jen , DAMON, Philippe , VAIDHYANATHAN, Natarajan , VERPLANKEN, Fabrice , VERRILLI, Colin Beaton
IPC分类号： H04L12/413 , H04L29/06
CPC分类号： H04L12/413 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/22 , H04L69/324
摘要： A system and method for reducing latency in a host Ethernet adapter (HEA) includes the following. First, the HEA receives a packet with an internet protocol (IP) header and data in the HEA (200) . The HEA parses a connection identifier from the IP header (205) and accesses a negative cache in the HEA (220) to determine if the connection identifier is not in a memory external to the HEA (240) . The HEA applies a default treatment to the packet (245) if the connection identifier is not in the memory, thereby reducing latency by decreasing access to the memory.
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公开(公告)号：EP1384354A2
公开(公告)日：2004-01-28
申请号：EP02719909.0
申请日：2002-01-31
发明人： CALVIGNAC, Jean, Louis , GOETZINGER, William, John , HANDLOGTEN, Glen, Howard , HEDDES, Marco, C. , LOGAN, Joseph, Franklin , MIKOS, James, Francis , NORGAARD, David, Alan , VERPLANKEN, Fabrice
CPC分类号： H04L12/5601 , H04L2012/5636 , H04L2012/5679 , H04L2012/5685
摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.
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公开(公告)号：EP1864465B1
公开(公告)日：2013-05-08
申请号：EP06725061.3
申请日：2006-03-15
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公开(公告)号：EP1875678A1
公开(公告)日：2008-01-09
申请号：EP06708770.0
申请日：2006-03-15
发明人： BASSO, Claude , CALVIGNAC, Jean , CHANG, Chih-Jen , VAIDHYANATHAN, Natarajan , DAMON, Philippe , VERPLANKEN, Fabrice , VERRILLI, Colin Beaton
CPC分类号： H04L12/40032 , H04L12/413 , H04L49/90 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/18 , H04L69/323 , H04L69/324
摘要： A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
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公开(公告)号：EP1864463A1
公开(公告)日：2007-12-12
申请号：EP06708769.2
申请日：2006-03-15
发明人： BASSO, Claude , CALVIGNAC, Jean , CHANG, Chih-jen , DAMON, Philippe , VAIDHYANATHAN, Natarajan , VERPLANKEN, Fabrice , VERRILLI, Colin Beaton
IPC分类号： H04L29/06
CPC分类号： H04L12/413 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/22 , H04L69/324
摘要： A system and method for reducing latency in a host Ethernet adapter (HEA) includes the following. First, the HEA receives a packet with an internet protocol (IP) header and data in the HEA (200) . The HEA parses a connection identifier from the IP header (205) and accesses a negative cache in the HEA (220) to determine if the connection identifier is not in a memory external to the HEA (240) . The HEA applies a default treatment to the packet (245) if the connection identifier is not in the memory, thereby reducing latency by decreasing access to the memory.
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7.发明公开
公开(公告)号：EP1864444A1
公开(公告)日：2007-12-12
申请号：EP06708771.8
申请日：2006-03-15
发明人： ARIMILLI, Ravi Kumar , CALVIGNAC, Jean , BASSO, Claude , CHANG, Chih-jen , DAMON, Philippe , FUHS, Ronald Edward , SHARMA, Satya Prakash , VAIDHYANATHAN, Natarajan , VERPLANKEN, Fabrice , VERRILLI, Colin Beaton
IPC分类号： H04L12/413 , H04L29/06
CPC分类号： H04L12/413 , H04L12/40032 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/324
摘要： An Ethernet adapter is disclosed. The Ethernet adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a demultiplexing mechanism to allow for partitioning of the processor. A Host Ethernet Adapter (HEA) is an integrated Ethernet adapter providing a new approach to Ethernet and TCP acceleration. A set of TCP/IP acceleration features have been introduced in a toolkit approach: Servers TCP/IP stacks use these accelerators when and as required. The interface between the server and the network interface controller has been streamlined by bypassing the PCI bus. The HEA supports network virtualization. The HEA can be shared by multiple OSs providing the essential isolation and protection without affecting its performance.
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8.发明授权APPARATUS AND METHOD FOR EFFICIENTLY SHARING MEMORY BANDWIDTH IN A NETWORK PROCESSOR 有权DEVICE AND METHOD FOR内存带宽在网络处理器有效配置
公开(公告)号：EP1374072B1
公开(公告)日：2005-07-27
申请号：EP02708513.3
申请日：2002-03-28
发明人： BARRI, Peter , CALVIGNAC, Jean , HEDDES, Marco c/o IBM United Kingdom Limited , LOGAN, Joseph , NIEMEGEERS, Alex , VERPLANKEN, Fabrice , VRANA, Miroslav
IPC分类号： G06F13/16
CPC分类号： G06F13/18 , G06F13/161
摘要： A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.
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公开(公告)号：EP1384354B1
公开(公告)日：2012-07-25
申请号：EP02719909.0
申请日：2002-01-31
发明人： CALVIGNAC, Jean, Louis , GOETZINGER, William, John , HANDLOGTEN, Glen, Howard , HEDDES, Marco, C. , LOGAN, Joseph, Franklin , MIKOS, James, Francis , NORGAARD, David, Alan , VERPLANKEN, Fabrice
CPC分类号： H04L12/5601 , H04L2012/5636 , H04L2012/5679 , H04L2012/5685
摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.
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公开(公告)号：EP1864465A1
公开(公告)日：2007-12-12
申请号：EP06725061.3
申请日：2006-03-15
发明人： CALVIGNAC, Jean , BASSO, Claude , KIEL, Harvey Gene , VERPLANKEN, Fabrice , VAIDHYANATHAN, Natarajan , FUHS, Ronald Edward , DAMON, Philippe , CHANG, Chih-jen , LUCKE, Alan Kyle , VERRILLI, Colin Beaton
摘要： Providing communications between operating system partitions and a computer network. In one aspect, an apparatus for distributing network communications among multiple operating system partitions includes a physical port allowing communications between the network and the computer system, and logical ports associated with the physical port, where each logical port is associated with one of the operating system partitions. Each of the logical ports enables communication between a physical port and the associated operating system partition and allows configurability of network resources of the system. Other aspects include a logical switch for logical and physical ports, and packet queues for each connection and for each logical port.
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