公开(公告)号：EP1433263A2

公开(公告)日：2004-06-30

申请号：EP02799650.3

申请日：2002-09-26

申请人： Koninklijke Philips Electronics N.V. ,  PHILIPS ELECTRONICS NORTH AMERICA CORPORATION

发明人： VAIDYANATHAN, Krishnamurthy ,  KRISHNAMACHARI, Santhana ,  VANDERSCHAAR, Mihaela

IPC分类号： H04B1/00

CPC分类号： H04B1/0003 ,  H04B1/406 ,  H04L69/32

摘要： A reconfigurable multi-media system, method and device provides monitoring and reconfiguration of a plurality of communication layers of a communications stack to dynamically reconfigure the modulation and coding of software defined radio (SDR) .The system includes a software object radio (SWR) library having reconfigurable object specification, design and performance parameters, the SWR is adapted for at least one of transmitting and receiving multi-media content via wireless communication; a controller in communication with the SWR library; a power management device module in communication with said controller; a reconfigurable encoder/decoder in communication with said controller to provide the SWR with dynamic coding information for modulation; a TCP/IP interface in communication with said reconfigurable encoder/decoder and said controller; and an application layer comprising a link layer and a reconfigurable physical layer in communication with each other and said controller, the physical layer adapted for communication with a channel, and the application layer including at least one driver for multimedia delivery. The controller monitors the physical layer and link layer information and the reconfigurable encoder/decoder dynamically reconfigures modulation and coding of multi-media content according to a cross-layer optimization approach.

公开(公告)号：EP1433263B1

公开(公告)日：2006-10-04

申请号：EP02799650.3

申请日：2002-09-26

申请人： Koninklijke Philips Electronics N.V. ,  PHILIPS ELECTRONICS NORTH AMERICA CORPORATION

发明人： VAIDYANATHAN, Krishnamurthy ,  KRISHNAMACHARI, Santhana ,  VANDERSCHAAR, Mihaela

IPC分类号： H04B1/00

CPC分类号： H04B1/0003 ,  H04B1/406 ,  H04L69/32

摘要： A reconfigurable multi-media system, method and device provides monitoring and reconfiguration of a plurality of communication layers of a communications stack to dynamically reconfigure the modulation and coding of software defined radio (SDR) .The system includes a software object radio (SWR) library having reconfigurable object specification, design and performance parameters, the SWR is adapted for at least one of transmitting and receiving multi-media content via wireless communication; a controller in communication with the SWR library; a power management device module in communication with said controller; a reconfigurable encoder/decoder in communication with said controller to provide the SWR with dynamic coding information for modulation; a TCP/IP interface in communication with said reconfigurable encoder/decoder and said controller; and an application layer comprising a link layer and a reconfigurable physical layer in communication with each other and said controller, the physical layer adapted for communication with a channel, and the application layer including at least one driver for multimedia delivery. The controller monitors the physical layer and link layer information and the reconfigurable encoder/decoder dynamically reconfigures modulation and coding of multi-media content according to a cross-layer optimization approach.

公开(公告)号：EP1466265A2

公开(公告)日：2004-10-13

申请号：EP02765239.5

申请日：2002-09-11

申请人： Koninklijke Philips Electronics N.V.

发明人： BURNS, Geoffrey, F. ,  VAIDYANATHAN, Krishnamurthy

IPC分类号： G06F15/80

CPC分类号： G06F9/30098 ,  G06F17/15

摘要： A component architecture for digital signal processing is presented. A two dimensional reconfigureable array of identical processors, where each processor communicates with its nearest neighbors, provides a simple and power-efficient platform to which convolutions, finite impulse response ('FIR') filters, and adaptive finite impulse response filters can be mapped. An adaptive FIR can be realized by downloading a simple program to each cell. Each program specifies periodic arithmetic processing for local tap updates, coefficient updates, and communication with nearest neighbors. During steady state processing, no high bandwidth communication with memory is required.This component architecture may be interconnected with an external controller, or general purpose digital signal processor, either to provide static configuration or else supplement the steady state processing.

公开(公告)号：EP1425902A2

公开(公告)日：2004-06-09

申请号：EP01272743.4

申请日：2001-12-11

申请人： Koninklijke Philips Electronics N.V.

发明人： BURNS, Geoffrey, F. ,  VAIDYANATHAN, Krishnamurthy

IPC分类号： H04N5/00

CPC分类号： H04N21/4382 ,  H04N19/467

摘要： A multi-standard channel decoder for real-time digital broadcast reception has a plurality of processors connected to a sample-based communication unit for sample-based processing and connected to a block-based communication unit for block-based processing. The channel decoder is able to use the same processors to channel decode sample-based transmissions such as 8-VSB broadcasts and block-based transmissions such as COFDM broadcasts.

公开(公告)号：EP1356650B1

公开(公告)日：2009-09-30

申请号：EP01273330.9

申请日：2001-12-19

申请人： Koninklijke Philips Electronics N.V.

发明人： VAIDYANATHAN, Krishnamurthy

IPC分类号： H04L27/00 ,  H04L27/06

CPC分类号： H04L27/0014 ,  H04L27/066 ,  H04L2027/0065

摘要： There is disclosed an improved system and method for providing frequency domain synchronization for a single carrier signal such as a vestigial sideband signal. The system comprises a synchronization circuit that is capable of obtaining a coarse frequency estimate of the single carrier signal and a fine frequency estimate of the single carrier signal. The system also comprises a three state machine for obtaining an accurate frequency estimate from three separately obtained frequency estimates. The system also comprises a DC estimator circuit that is capable of providing a time domain DC estimate. The system provides a pilot carrier recovery circuit for single carrier signals that has a linear transfer function.

公开(公告)号：EP1459168A1

公开(公告)日：2004-09-22

申请号：EP02785822.4

申请日：2002-12-03

申请人： Koninklijke Philips Electronics N.V.

发明人： VAIDYANATHAN, Krishnamurthy ,  BURNS, Geoffrey, F.

IPC分类号： G06F9/30 ,  G06F9/355

CPC分类号： G06F9/30098 ,  G06F9/3013 ,  G06F9/30134

摘要： A delay addressed data path register file is designed for use in a programmable processor making up a cell in a multi-processor or array signal processing system. The delay addressable register file is particularly useful in, inter alia, adaptive filters where the filter update latency is variable, interpolation filters where the interpolation factor needs to be programmable, and decimation filters where the decimation factor needs to be programmable. The programmability is achieved in an efficient manner, reducing the number of cycles required to perform this task. A single parameter, the 'delay limit' value, is programmed at start-up, setting up an internal delay-line within the register file of the processor. Thus, any of the delayed registers can be addressed by specifying the delay index during run-time. The delay line advances one location, modulo 'delay-limit', when the processing loop starts a new iteration.

公开(公告)号：EP1573529A2

公开(公告)日：2005-09-14

申请号：EP03812646.2

申请日：2003-12-08

申请人： Koninklijke Philips Electronics N.V.

发明人： VAIDYANATHAN, Krishnamurthy ,  BURNS, Geoffrey, Francis

IPC分类号： G06F9/445

CPC分类号： G06F9/445 ,  G06F15/177 ,  G06F15/8023

摘要： A method (400) and apparatus (100) are disclosed for storing the software specifications (320) for each processor (110) in a multi-processor system (100). The disclosed storage technique reduces the total memory space that is required to store the configuration information for each processor (110) and does not require a linear scaling of the memory size when the number of processors increases. Each unique software specification (320) is stored in memory and a pointer (310) is stored for each processor (110) that identifies the corresponding location in memory (140') of the configuration information for the processor (110). The size of the memory area that stores the pointers (310) for each processor (110) still has a linear relationship with the number of processors (110). The size of the memory area (140') that stores the unique software specifications (320) is independent of the number of processors (110).

公开(公告)号：EP1356650A1

公开(公告)日：2003-10-29

申请号：EP01273330.9

申请日：2001-12-19

申请人： Koninklijke Philips Electronics N.V.

发明人： VAIDYANATHAN, Krishnamurthy

IPC分类号： H04L27/00 ,  H04L27/06

CPC分类号： H04L27/0014 ,  H04L27/066 ,  H04L2027/0065

摘要： There is disclosed an improved system and method for providing frequency domain synchronization for a single carrier signal such as a vestigial sideband signal. The system comprises a synchronization circuit that is capable of obtaining a coarse frequency estimate of the single carrier signal and a fine frequency estimate of the single carrier signal. The system also comprises a three state machine for obtaining an accurate frequency estimate from three separately obtained frequency estimates. The system also comprises a DC estimator circuit that is capable of providing a time domain DC estimate. The system provides a pilot carrier recovery circuit for single carrier signals that has a linear transfer function.

公开(公告)号：EP1332613A1

公开(公告)日：2003-08-06

申请号：EP01988000.4

申请日：2001-10-09

申请人： Koninklijke Philips Electronics N.V.

发明人： GAY-BELLILE, Olivier ,  MARCHAL, Xavier ,  BURNS, Geoffrey, F. ,  VAIDYANATHAN, Krishnamurthy

IPC分类号： H04N5/44 ,  H04N5/445

CPC分类号： H04L1/0045 ,  H04L1/0052 ,  H04L25/03057 ,  H04L25/03159 ,  H04L2025/0349 ,  H04L2025/03522 ,  H04N5/4401 ,  H04N5/46 ,  H04N21/4382 ,  H04N21/44209 ,  H04N21/4435

摘要： The invention relates to a multi-standard digital receiver, in a digital video transmission system. It comprises a channel decoder for protecting a transmitted signal against channel transmission errors, the channel decoder comprising: a set of co-processors including at least 3 clusters of programmable co-processors for executing the functions of a digital front-end block (DFE), a channel correction block (CHN) and a forward error correction block (FEC), respectively; a general purpose processor (DSP) for managin g control, synchronization and configuration of the channel decoder; and a memory (SM) shared between the clusters and the general purpose processor.

公开(公告)号：EP1709549A2

公开(公告)日：2006-10-11

申请号：EP05702752.6

申请日：2005-01-21

申请人： Koninklijke Philips Electronics N.V.

发明人： VAIDYANATHAN, Krishnamurthy ,  WITTIG, Karl, R. ,  BURNS, Geoffrey, F.

IPC分类号： G06F15/78

CPC分类号： G06F15/7867 ,  H04W88/08

摘要： A dynamically reconfigurable signal processing apparatus (158c) is disclosed. The signal processing apparatus (158c) includes at least one system controller (170) for detecting a change of state in a high speed digital communication system (10). Responsive to the change of state, in one embodiment, signal processing function code is downloaded, in real-time or in near real-time, from an external memory (130) to be processed in an array-type processor (120). In another embodiment, signal processing function code for a plurality of signal processing functions are pre-stored in the array­type processor (120) and are switch selectable in response to a change of system state thereby obviating the need to download signal processing function code.