公开(公告)号：EP2340540A1

公开(公告)日：2011-07-06

申请号：EP09793198.4

申请日：2009-09-30

申请人： LSI Corporation

发明人： BURGER, Harley, F., Jr. ,  HARATSCH, Erich, F. ,  IVKOVIC, Milos ,  KRACHKOVSKY, Victor ,  MILADINOVIC, Nenad ,  VITYAEV, Andrei ,  YEN, Johnson

IPC分类号： G11C16/26 ,  G11C16/34 ,  G11C7/10 ,  G11C11/56

CPC分类号： G11C16/26 ,  G06F11/1012 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/2022 ,  G11C7/02 ,  G11C7/04 ,  G11C11/16 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5634

摘要： Methods and apparatus are provided for soft data generation for memory devices using reference cells. At least one soft data value is generated in a memory device by writing a known data to one or more reference cells; reading one or more of the reference cells; obtaining a read statistic based on the read one or more reference cells; and obtaining the at least one soft data value based on the obtained read statistic. The read statistics can optionally be obtained for one or more desired locations of a memory array; or for a given pattern, PATT, in one or more aggressor cells. The read statistic can optionally comprise asymmetric statistics obtained for a plurality of possible values.

摘要翻译： 提供的方法和装置，用于软数据生成用于基于性能因素调节的存储器装置。 用于存储器装置中产生至少一个软数据值，检查作为快闪存储器装置，通过获得至少一个读取值; 以及基于所获得的至少一个读取值和根据所述存储装置的一个或多个性能因素调整所述软数据值。 所述读取值可以是软或硬数据。 可能的性能因素包括耐力，读取周期数，保持时间，温度，工艺角，单元间干扰影响，位置和侵略者单元图案。 因此一个或多个图案依赖性和/或特定于位置的性能因素可被考虑。 所产生的软数据值可以是用于产生一个或更多个对数似然比，或者可以是对数似然比自己的软读取值。

公开(公告)号：EP2311041A1

公开(公告)日：2011-04-20

申请号：EP09790691.1

申请日：2009-07-21

申请人： LSI Corporation

发明人： HARATSCH, Erich, F. ,  IVKOVIC, Milos ,  KRACHKOVSKY, Victor ,  MILADINOVIC, Nenad ,  VITYAEV, Andrei ,  YEN, Johnson

IPC分类号： G11C16/10 ,  G11C16/34 ,  G11C11/56

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： Methods and apparatus are provided for programming multiple program values per signal level in flash memories. A flash memory device having a plurality of program values is programmed by programming the flash memory device for a given signal level, wherein the programming step comprises a programming phase and a plurality of verify phases. In another variation, a flash memory device having a plurality of program values is programmed, and the programming step comprises a programming phase and a plurality of verify phases, wherein at least one signal level comprises a plurality of the program values. The signal levels or the program values (or both) can be represented using one or more of a voltage, a current and a resistance.

公开(公告)号：EP2308053A1

公开(公告)日：2011-04-13

申请号：EP09774392.6

申请日：2009-06-30

申请人： LSI Corporation

发明人： HARATSCH, Erich, F. ,  IVKOVIC, Milos ,  KRACHKOVSKY, Victor ,  MILADINOVIC, Nenad ,  VITYAEV, Andrei ,  YEN, Johnson

IPC分类号： G11C16/10 ,  G11C11/56

CPC分类号： G11C16/3427 ,  G06F11/1072 ,  G11C5/00 ,  G11C7/02 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3418

摘要： Methods and apparatus are provided for write-side intercell interference mitigation in flash memories. A flash memory device is written by obtaining program data to be written to at least one target cell in the flash memory; obtaining one or more bits of program data for at least one aggressor cell to be programmed later than the target cell: and precompensating for intercell interference for the target cell by generating precompensated program values. The aggressor cells comprise one or more cells adjacent to the target cell, such as adjacent cells in a same wordline as the target cell and/or cells in an upper or lower adjacent wordline to the target cell. The precompensated program values for the target cell are optionally provided to the flash memory.

摘要翻译： 在闪速存储器提供用于读出侧的小区间干扰抑制方法和装置。 快闪存储器装置是通过获取用于至少一个目标单元的读取值读取; 获得存储在至少一个入侵单元表示电压的值没有目标小区后所编程; 用于从所述至少一个入侵单元中的目标小区确定性采矿间干扰; 并获得新的读取值可以做到通过去除的至少一个目标单元的读取值确定性开采小区间干扰补偿小区间干扰。 新的读取值可以选择性地提供给解码器。 在迭代实现中，一个或多个小区间干扰抑制参数可以如果解码错误的发生来调节。

公开(公告)号：EP2308058B1

公开(公告)日：2016-01-27

申请号：EP09774391.8

申请日：2009-06-30

申请人： LSI Corporation

发明人： HARATSCH, Erich, F. ,  IVKOVIC, Milos ,  KRACHKOVSKY, Victor ,  MILADINOVIC, Nenad ,  VITYAEV, Andrei ,  YEN, Johnson

IPC分类号： G11C7/02 ,  G11C16/10 ,  G11C7/10 ,  G11C11/56 ,  G11C16/34 ,  G06F11/10 ,  G11C5/00

CPC分类号： G11C16/3427 ,  G06F11/1072 ,  G11C5/00 ,  G11C7/02 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3418

公开(公告)号：EP2308056A1

公开(公告)日：2011-04-13

申请号：EP09774398.3

申请日：2009-06-30

申请人： LSI Corporation

发明人： HARATSCH, Erich, F. ,  IVKOVIC, Milos ,  KRACHKOVSKY, Victor ,  MILADINOVIC, Nenad ,  VITYAEV, Andrei ,  YEN, Johnson

IPC分类号： G11C16/10 ,  G11C11/56

CPC分类号： G11C16/3427 ,  G06F11/1072 ,  G11C5/00 ,  G11C7/02 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3418

摘要： Methods and apparatus are provided for soft demapping and intercell interference mitigation in flash memories. In one variation, a target cell in a flash memory device capable of storing at least two data levels, s, per cell is read by obtaining a measured read value, r, for at least one target cell in the flash memory; obtaining a value, h, representing data stored for at least one aggressor cell in the flash memory; selecting one or more probability density functions based on a pattern of values stored in at least a portion of the flash memory, wherein the probability density functions comprises pattern-dependent disturbance of one or more aggressor cells on the at least one target cell in the flash memory; evaluating at least one selected probability density function based on the measured read value, r; and computing one or more log likelihood ratios based on a result of the evaluating step.

摘要翻译： 在闪速存储器提供用于读出侧的小区间干扰抑制方法和装置。 快闪存储器装置是通过获取用于至少一个目标单元的读取值读取; 获得存储在至少一个入侵单元表示电压的值没有目标小区后所编程; 用于从所述至少一个入侵单元中的目标小区确定性采矿间干扰; 并获得新的读取值可以做到通过去除的至少一个目标单元的读取值确定性开采小区间干扰补偿小区间干扰。 新的读取值可以选择性地提供给解码器。 在迭代实现中，一个或多个小区间干扰抑制参数可以如果解码错误的发生来调节。

公开(公告)号：EP2308055A1

公开(公告)日：2011-04-13

申请号：EP09774395.9

申请日：2009-06-30

申请人： LSI Corporation

发明人： GRAEF, Nils ,  HARATSCH, Erich, F. ,  IVKOVIC, Milos ,  KRACHKOVSKY, Victor ,  VITYAEV, Andrei ,  YEN, Johnson

IPC分类号： G11C16/10 ,  G11C11/56 ,  G11C7/10 ,  H03M13/00

CPC分类号： G11C16/3427 ,  G06F11/1072 ,  G11C5/00 ,  G11C7/02 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3418

摘要： Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell.

摘要翻译： 在闪速存储器提供用于读出侧的小区间干扰抑制方法和装置。 快闪存储器装置是通过获取用于至少一个目标单元的读取值读取; 获得存储在至少一个入侵单元表示电压的值没有目标小区后所编程; 用于从所述至少一个入侵单元中的目标小区确定性采矿间干扰; 并获得新的读取值可以做到通过去除的至少一个目标单元的读取值确定性开采小区间干扰补偿小区间干扰。 新的读取值可以选择性地提供给解码器。 在迭代实现中，一个或多个小区间干扰抑制参数可以如果解码错误的发生来调节。

公开(公告)号：EP2340541A1

公开(公告)日：2011-07-06

申请号：EP09793200.8

申请日：2009-09-30

申请人： LSI Corporation

发明人： HARATSCH, Erich, F. ,  IVKOVIC, Milos ,  KRACHKOVSKY, Victor ,  MILADINOVIC, Nenad ,  VITYAEV, Andrei ,  WILLIAMSON, Clifton ,  YEN, Johnson

IPC分类号： G11C16/34 ,  G11C16/26 ,  G11C7/10 ,  G11C11/56

CPC分类号： G11C16/26 ,  G06F11/1012 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/2022 ,  G11C7/02 ,  G11C7/04 ,  G11C11/16 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5634

摘要： Methods and apparatus for soft data generation for memory devices using decoder performance feedback. At least one soft data value is generated in a memory device, by obtaining performance feedback from a decoder; obtaining an error statistic based on the performance feedback; and generating the at least one soft data value based on the obtained error statistic. The performance feedback comprises one or more of decoded bits, a number of erroneous bits based on data decoded by the decoder and a number of unsatisfied parity checks.

摘要翻译： 提供的方法和装置，用于软数据生成用于基于性能因素调节的存储器装置。 用于存储器装置中产生至少一个软数据值，检查作为快闪存储器装置，通过获得至少一个读取值; 以及基于所获得的至少一个读取值和根据所述存储装置的一个或多个性能因素调整所述软数据值。 所述读取值可以是软或硬数据。 可能的性能因素包括耐力，读取周期数，保持时间，温度，工艺角，单元间干扰影响，位置和侵略者单元图案。 因此一个或多个图案依赖性和/或特定于位置的性能因素可被考虑。 所产生的软数据值可以是用于产生一个或更多个对数似然比，或者可以是对数似然比自己的软读取值。

公开(公告)号：EP2340539A1

公开(公告)日：2011-07-06

申请号：EP09793196.8

申请日：2009-09-30

申请人： LSI Corporation

发明人： HARATSCH, Erich, F. ,  IVKOVIC, Milos ,  KRACHKOVSKY, Victor ,  MILADINOVIC, Nenad ,  VITYAEV, Andrei ,  WILLIAMSON, Clifton ,  YEN, Johnson

IPC分类号： G11C16/26 ,  G11C16/34 ,  G11C7/10 ,  G11C11/56

CPC分类号： G11C16/26 ,  G06F11/1012 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/2022 ,  G11C7/02 ,  G11C7/04 ,  G11C11/16 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5634

摘要： Methods and apparatus are provided for soft data generation for memory devices. At least one soft data value is generated for a memory device, by obtaining at least one hard read value; and generating the soft data value associated with the at least one hard read value based on statistics for reading the hard read value. The hard read value may be one or more of data bits, voltage levels, current levels and resistance levels. The generated soft data value may be one or more of (i) a soft read value that is used to generate one or more log likelihood ratios, and (ii) one or more log likelihood ratios. The statistics comprise one or more of bit-based statistics and cell-based statistics. The statistics may also optionally comprise pattern-dependent disturbance of at least one aggressor cell on the target cell, as well as location-specific statistics. At least one soft data value can be generated for a memory device, by obtaining a soft read value; and generating the soft data value associated with the soft read value based on statistics for reading the soft read value, wherein the statistics comprise one or more of location-specific statistics and pattern-dependent statistics.

公开(公告)号：EP2308058A1

公开(公告)日：2011-04-13

申请号：EP09774391.8

申请日：2009-06-30

申请人： LSI Corporation

发明人： HARATSCH, Erich, F. ,  IVKOVIC, Milos ,  KRACHKOVSKY, Victor ,  MILADINOVIC, Nenad ,  VITYAEV, Andrei ,  YEN, Johnson

IPC分类号： G11C16/26 ,  G11C16/34 ,  G11C11/56

CPC分类号： G11C16/3427 ,  G06F11/1072 ,  G11C5/00 ,  G11C7/02 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3418

摘要： Methods and apparatus are provided for read-side intercell interference mitigation in flash memories, A flash memory device is read by obtaining a read value for at least one target cell; obtaining a value representing a voltage stored in at least one aggressor cell that was programmed after the target cell; determining intercell interference for the target cell from the at least one aggressor cell; and obtaining a new read value that compensates for the intercell interference by removing the determined intercell interference from the read value for the at least one target cell. The new read value can optionally be provided to a decoder. In an iterative implementation, one or more intercell interference mitigation parameters can be adjusted if a decoding error occurs.