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1.发明公开On-line testing of the programmable interconnect network in field programmable gate arrays 有权在线客户计算机软件程序软件在Gineranordnung
公开(公告)号：EP1089084A1
公开(公告)日：2001-04-04
申请号：EP00308136.1
申请日：2000-09-18
IPC分类号： G01R31/3185 , G11C29/00
CPC分类号： G01R31/318519 , G11C29/12 , H01L2924/0002 , H01L2924/00
摘要： A method of self-testing the programmable routing network in a field programmable gate array (FPGA) during normal on-line operation includes configuring the FPGA into an initial self-testing area and a working area. The initial self-testing area is preferably configured to include an horizontal self-testing area primarily for testing horizontal wire segments and a vertical self-testing area primarily for testing vertical wire segments. Programmable logic blocks located within the self-testing areas are configured to function as a test pattern generator and an output response analyzer, and a portion of the programmable routing resources within the self-testing areas is configured as groups of wires under test. An exhaustive set of test patterns generated by the test pattern generator is applied to the groups of wires under test which are repeatedly reconfigured in order to completely test the programmable routing resources within the self-testing areas. The outputs of the groups of wires under test are compared by the output response analyzer and resultant fault status data for each group of wires under test is received by a controller in communication with a memory for storing the fault status data. After completely testing the programmable routing resources in one of the initial self-testing areas, the FPGA is reconfigured such that a portion of the working area becomes a subsequent self-testing area and at least a portion of one of the initial self-testing areas replaces that portion of the working area. In other words, the self-testing areas rove around the FPGA repeating the steps of testing and reconfiguring until the entire FPGA has undergone testing or continuously.
摘要翻译： 在正常在线操作期间，在现场可编程门阵列（FPGA）中对可编程路由网络进行自检的方法包括将FPGA配置为初始自检区域和工作区域。 初始自检区域优选地被配置为包括主要用于测试水平线段的水平自检区域和主要用于测试垂直线段的垂直自检区域。 位于自检区域内的可编程逻辑块被配置为用作测试模式发生器和输出响应分析器，并且自测试区域内的一部分可编程路由资源被配置为被测电线组。 由测试模式发生器生成的一组穷举的测试图案被应用于被重复重新配置的线路组，以便完全测试自测试区域内的可编程路由资源。 通过输出响应分析器比较所测试的电线组的输出，并且与用于存储故障状态数据的存储器通信的控制器接收每组待测电线的合成故障状态数据。 在对初始自检区域之一中的可编程路由资源进行完全测试之后，重新配置FPGA，使得工作区域的一部分成为随后的自检区域，并且其中一个初始自检区域的至少一部分 取代了该部分工作区域。 换句话说，FPGA上的自检区域重复测试和重新配置的步骤，直到整个FPGA经过测试或连续进行。
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2.发明公开On-line fault tolerant operation via incremental reconfiguration of field programmable gate arrays 审中-公开通过现场可编程门阵列的重构增量在线容错操作
公开(公告)号：EP1170666A3
公开(公告)日：2002-06-26
申请号：EP01304817.8
申请日：2001-05-31
IPC分类号： G06F11/20 , G01R31/3185
CPC分类号： G01R31/318519 , G06F11/1428
摘要： A method of fault tolerant operation of field programmable gate arrays (FPGAs) utilizing incremental reconfiguration during normal on-line operation includes configuring an FPGA into initial self-testing areas and a working area. Within the self-testing areas, programmable logic blocks (PLBs) of the FPGA are tested for faults. Upon the detection of one or more faults within the PLBs, the faulty PLBs are isolated and their modes of operation exhaustively tested. Partially faulty PLBs are allowed to continue operation in a diminished capacity as long as the faulty modes of operation do not prevent the PLBs from performing non-faulty system functions. After testing the programmable logic blocks in the initial self-testing areas, the FPGA is reconfigured such that a portion of the working area becomes a subsequent self-testing area and at least a portion of the initial self-testing area replaces that portion of the working area. In other words, the self-testing area roves around the FPGA repeating the steps of testing and reconfiguring until the entire FPGA has undergone testing, or continuously.
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3.发明授权On-line testing of the programmable interconnect network in field programmable gate arrays 有权在现场可编程门阵列的可编程互连网络的在线测试
公开(公告)号：EP1089084B1
公开(公告)日：2004-05-12
申请号：EP00308136.1
申请日：2000-09-18
IPC分类号： G01R31/3185 , G11C29/00
CPC分类号： G01R31/318519 , G11C29/12 , H01L2924/0002 , H01L2924/00
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4.发明公开On-line fault tolerant operation via incremental reconfiguration of field programmable gate arrays 审中-公开在线fehlertoleranter Betrieb durch inkrementelle Rekonfigurierung eines feldprogrammierbaren Gatterfeldes
公开(公告)号：EP1170666A2
公开(公告)日：2002-01-09
申请号：EP01304817.8
申请日：2001-05-31
IPC分类号： G06F11/20 , G01R31/3185
CPC分类号： G01R31/318519 , G06F11/1428
摘要： A method of fault tolerant operation of field programmable gate arrays (FPGAs) utilizing incremental reconfiguration during normal on-line operation includes configuring an FPGA into initial self-testing areas and a working area. Within the self-testing areas, programmable logic blocks (PLBs) of the FPGA are tested for faults. Upon the detection of one or more faults within the PLBs, the faulty PLBs are isolated and their modes of operation exhaustively tested. Partially faulty PLBs are allowed to continue operation in a diminished capacity as long as the faulty modes of operation do not prevent the PLBs from performing non-faulty system functions. After testing the programmable logic blocks in the initial self-testing areas, the FPGA is reconfigured such that a portion of the working area becomes a subsequent self-testing area and at least a portion of the initial self-testing area replaces that portion of the working area. In other words, the self-testing area roves around the FPGA repeating the steps of testing and reconfiguring until the entire FPGA has undergone testing, or continuously. Prior to relocating the initial self-testing areas, the initial self-testing areas are reconfigured to replace unusable faulty PLBs with spare PLBs. Spare PLBs are initially allocated throughout the working area. Specifically, each operational PLB within the working area is allocated an adjacent preferred spare PLB. Predetermined configurations of the FPGA utilizing the preferred spares are used to avoid the faulty PLBs. If the initially allocated spares are incapable of utilization, then a subsequent portion of the PLBs within the working area are allocated as spares and new replacement configurations determined. As the number of spare PLBs is diminished over time, additional spare PLBs are at some point necessarily removed from the self-testing areas. In this manner, the testing and roving capabilities of the self-testing area are also inevitably diminished. Eventually, roving, testing, and even operation of the FPGA will cease.
摘要翻译： 在正常在线操作期间利用增量重新配置的现场可编程门阵列（FPGA）的容错操作的方法包括将FPGA配置为初始自检区域和工作区域。 在自检区域内，FPGA的可编程逻辑块（PLB）被测试出故障。 在检测到PLB中的一个或多个故障之后，故障的PLB被隔离，并且其操作模式被彻底测试。 只要有故障的操作模式不能阻止PLB执行无故障的系统功能，部分故障的PLB就能够在能力下降的情况下继续运行。 在对初始自检区域中的可编程逻辑块进行测试之后，重新配置FPGA，使得工作区域的一部分成为随后的自检区域，并且初始自检区域的至少一部分取代了 工作区域。 换句话说，自检区域遍布FPGA，重复测试和重新配置的步骤，直到整个FPGA进行了测试，或者连续进行。 在重新设置初始自检区域之前，将重新配置初始自检区域，以用备用的PLB来替换不可用的故障小巴。 备用小巴最初分配在整个工作区。 具体来说，工作区域内的每个操作PLB被分配相邻的优选备用PLB。 使用优选备件的FPGA的预定配置用于避免故障的PLB。 如果初始分配的备件不能使用，则将工作区域内的PLB的后续部分分配为备件，并确定新的替换配置。 由于备用小巴的数目随时间而减少，所以额外的备用小巴在某些时候一定会从自检地区移走。 以这种方式，自检区的测试和流动能力也不可避免地减少了。 最终，FPGA的漫游，测试甚至操作将会停止。
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公开(公告)号：EP0803814A1
公开(公告)日：1997-10-29
申请号：EP97302563.8
申请日：1997-04-15
IPC分类号： G06F11/263 , G01R31/3185
CPC分类号： G01R31/318552 , G01R31/318586
摘要： A method of increasing the testability of sequential circuit designs uses a clock transformation technique. Circuit states which are difficult to reach, but are nonetheless required to detect at least one fault of the circuit, are automatically identified. By way of illustration, estimations of joint line probabilities are compared with a preselected threshold value to identify hard-to-reach states. Then, commonly clocked flip-flops (18) which must be simultaneously assigned values in order to reach the identified states are partitioned into independently clocked (via TEST CONTROL INPUTS) groups of flip-flops. In this manner, hard-to-reach circuit states are transformed into easy-to-reach states, which, in turn, results in transforming difficult-to-detect faults into easy-to-detect faults.
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