SEMICONDUCTOR STORAGE DEVICE AND ITS MANUFACTURING METHOD
    2.
    发明公开
    SEMICONDUCTOR STORAGE DEVICE AND ITS MANUFACTURING METHOD 审中-公开
    HALBLEITERSPEICHERBAUSTEIN UND VERFAHREN ZU SEINER HERSTELLUNG

    公开(公告)号:EP1359622A4

    公开(公告)日:2008-04-09

    申请号:EP01273090

    申请日:2001-12-28

    摘要: A memory cell of a DRAM that is a semiconductor storage device has a bit line (21a) connected to a bit line plug (20b) and a local wiring (21b) on a first interlayer insulation film (18). The side face of a hard mask (37), an upper barrier metal (36), a Pt film, and a BST film (34) is overlaid with a conductor side wall (40) made of TiAlN. No contact is provided on the Pt film (35) which constitutes an upper electrode (35a), but the upper electrode (35a) is connected to an upper layer wiring (Cu wiring 42) by a conductor side wall (40), dummy lower electrode (33b), a dummy cell plug (30), and a local wiring (21b). Since the Pt film (35) is not exposed to a reductive atmosphere, a capacitor insulation film (34a) is prevented from deteriorating in characteristics.

    摘要翻译: 作为半导体存储器件的DRAM的存储单元具有连接到位线插塞(20b)的位线(21a)和第一层间绝缘膜(18)上的局部布线(21b)。 硬掩模(37),上阻挡金属(36),Pt膜和BST膜(34)的侧面覆盖有由TiAlN制成的导体侧壁(40)。 在构成上部电极(35a)的Pt膜(35)上没有设置接点,上部电极(35a)通过导体侧壁(40)与上层布线(Cu布线42)连接, 电极33b,虚设单元插头30以及局部布线21b。 由于Pt膜(35)不暴露于还原性气氛,因此可以防止电容器绝缘膜(34a)的特性恶化。