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公开(公告)号：EP0665653A3
公开(公告)日：1997-04-02
申请号：EP95100985.1
申请日：1995-01-25
发明人： Takeno, Hiroshi , Miyagoshi, Eiji , Imanishi, Hiroshi , Nakatani, Shintarou , Akiyama, Toshihide
IPC分类号： H03M7/42
CPC分类号： H03M7/425
摘要： 5 n7 A variable-length-code decoder of this invention decodes an input bit stream including an input bit string having a codeword of a fixed-length code and a plurality of codewords of variable-length codes combined in a predetermined format. The decoder includes: a shifter for shifting the input bit string by a desired number of bits; a pattern detector for detecting a specific pattern in the bit string, and outputting a detection signal; two code tables provided for the respective variable-length codes, each code table having the length of each codeword (codeword length) and the decoded-word corresponding to the codeword, and outputting a codeword length and a decoded-word of a corresponding codeword based on the bit string output from the shifter; a processor for storing the format of the input bit string, outputting the length of the fixed-length code and decoded data of the fixed-length code, and selecting, for each of the variable-length codewords, one of the code tables to which the variable-length codeword belongs to, based on the detection signal and the format; a codelength selector for selecting the codeword length or the fixed-length code, and for setting the shift amount for the input bit string in the shifter; and an output circuit for selectively outputting the decoded-word or the decoded data.
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公开(公告)号：EP0825781B1
公开(公告)日：2004-10-27
申请号：EP97113976.1
申请日：1997-08-13
发明人： Watabe, Akihiro , Miyagoshi, Eiji
IPC分类号： H04N7/50
CPC分类号： H04N19/427 , H04N19/423 , H04N19/61
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公开(公告)号：EP1098314A1
公开(公告)日：2001-05-09
申请号：EP99929804.5
申请日：1999-07-13
发明人： Miyagoshi, Eiji , Watabe, Akihiro
CPC分类号： G11B27/105 , G11B20/10 , G11B27/005 , G11B27/3036 , G11B2220/2562 , H04N5/783 , H04N9/8042 , H04N21/4334 , H04N21/4402 , H04N21/440281
摘要： A decoding device 1 decodes a bit stream including a plurality of packets. Data corresponding to an access unit includes a first data portion 150a-1 and a second data portion 150a-2 . The decoding device 1 includes a packet regeneration section 10 for receiving a first packet 130 and a second packet 130 following the first packet 130 , and when the first packet 130 includes the first data portion 150a-1 and the second packet 130 includes the second data portion 150a-2 , producing a new packet 164 including the data corresponding to the access unit by combining the first data portion 150a-1 and the second data portion 150a-2 . The decoding device 1 also includes a decoding section 40 for decoding the data corresponding to the access unit. The new packet 164 includes information indicating a length of the data corresponding to the access unit.
摘要翻译： 解码装置1对包括多个分组的比特流进行解码。 对应于访问单元的数据包括第一数据部分150a-1和第二数据部分150a-2。 解码装置1包括分组再生部10，用于接收第一分组130之后的第一分组130和第二分组130，并且当第一分组130包括第一数据部分150a-1，并且第二分组130包括第二数据 部分150a-2，通过组合第一数据部分150a-1和第二数据部分150a-2，产生包括对应于访问单元的数据的新分组164。 解码装置1还包括用于解码对应于访问单元的数据的解码部分40。 新分组164包括指示对应于该访问单元的数据的长度的信息。
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公开(公告)号：EP1630997A3
公开(公告)日：2006-04-19
申请号：EP05022673.7
申请日：1998-12-28
发明人： Yamaguchi, Ryoji , Miyagoshi, Eiji
CPC分类号： H04N21/4347 , H04J3/0608 , H04N19/70 , H04N21/236 , H04N21/4305 , H04N21/434
摘要： A coded signal reproduction apparatus comprising end code sequence detection means for detecting, from code sequences of coded data, a code sequence indicating the end of the coded data; and formatter means for adding a predetermined number of pseudo data to the rear of the code sequence indicating the end of the coded data so that the data bus width of pipeline transfer including the end of the coded data becomes equal to the bus width of pipeline transfer including other data, when a code sequence indicating the end of the code data is detected. Data transfers inside the pipeline in the reproduction apparatus can be performed to the end of coded data which is shorter than the data bus width in the pipeline. The coded signal reproduction apparatus inserts a specific code sequence in the last packet of the packet sequence before adding pseudo data.
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公开(公告)号：EP1630997A2
公开(公告)日：2006-03-01
申请号：EP05022673.7
申请日：1998-12-28
发明人： Yamaguchi, Ryoji , Miyagoshi, Eiji
CPC分类号： H04N21/4347 , H04J3/0608 , H04N19/70 , H04N21/236 , H04N21/4305 , H04N21/434
摘要： A formatter 2s13 is provided and, when a code sequence which matches a part ('00') of the head of a predetermined code sequence detected by a start code prefix detection unit 2s3, is detected, the start code prefix detection unit 2s3 detects the residual part ('00','00','01','E0') of the detected predetermined code sequence to detect a pattern of ('00','00','00'), and the formatter 2s13 outputs one ('00'). After the boundary of packets is defined, amongst data which are not transferred to a decoding buffer 2s9, data corresponding to code sequences other than the code sequence ('00','00','01','E0') indicating the packet boundary are output to the decoding buffer 2s9. Therefore, when separating a coded and multiplexed signal, control of an input buffer reading control circuit 2s4 is simplified, and thereby the hardware scale is reduced, resulting in an inexpensive apparatus for reproducing a digital code sequence.
摘要翻译： 格式化器2s13被提供，并且当检测到与由起始码前缀检测单元2s3检测到的预定码序列的头部的部分（'00'）匹配的码序列时，起始码前缀检测单元2s3检测 （'00'，'00'，'00'）的模式的剩余部分（'00'，'00'，'01'，'E0'），并且格式化器2s13输出一个 （ '00'）。 在确定了分组的边界之后，在未被传送到解码缓冲器2s9的数据中，与除指示分组的码序列（'00'，'00'，'01'，'E0'）以外的码序列相对应的数据 边界被输出到解码缓冲器2s9。 因此，当分离编码和多路复用信号时，输入缓冲器读取控制电路2s4的控制被简化，并且由此硬件规模减小，从而导致用于再现数字代码序列的廉价设备。
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公开(公告)号：EP0825781A2
公开(公告)日：1998-02-25
申请号：EP97113976.1
申请日：1997-08-13
发明人： Watabe, Akihiro , Miyagoshi, Eiji
IPC分类号： H04N7/50
CPC分类号： H04N19/427 , H04N19/423 , H04N19/61
摘要： A frame memory is provided which has five fields each having N slots, and three additional slots. Each slot has a storage capacity to store eight image lines. Four fields of the five fields serve to store motion compensation reference frames. The remaining one field and the three additional slots are used for B-picture interlace conversion. Disposed in a control unit are a slot control memory, a write slot pointer, and a read slot pointer. For an image output unit to acquire information from the frame memory in a correct slot order, the contents of the slot control memory are updated at the time of performing write operation to enter information into the frame memory by a bit stream analysis unit.
摘要翻译： 提供一个帧存储器，其具有五个场，每个场具有N个时隙，以及三个附加时隙。 每个插槽具有存储8个图像行的存储容量。 五个场中的四个场用于存储运动补偿参考帧。 剩余的一个场和三个附加时隙用于B图像交错转换。 在控制单元中设置有时隙控制存储器，写时隙指针和读槽指针。 对于图像输出单元，以正确的时隙顺序从帧存储器获取信息，在执行写入操作时更新时隙控制存储器的内容，以通过比特流分析单元将信息输入到帧存储器中。
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公开(公告)号：EP1443511A2
公开(公告)日：2004-08-04
申请号：EP03026070.7
申请日：2003-11-12
发明人： Miyagoshi, Eiji , Watabe, Akihiro
CPC分类号： H04N21/4424 , G11B20/00007 , G11B20/10 , G11B27/034 , G11B27/36 , G11B2020/00079 , G11B2220/216 , G11B2220/218 , G11B2220/2541 , G11B2220/2562 , G11B2220/2575 , H04N5/4401 , H04N5/76 , H04N5/781 , H04N5/85 , H04N9/8042 , H04N19/132 , H04N19/146 , H04N19/15 , H04N19/46 , H04N19/587 , H04N19/59 , H04N19/61 , H04N21/234363
摘要： When a digitized broadcast is recorded in a storage medium, a required capacity of the storage medium is firstly calculated on the basis of a bit-rate of digitized broadcast data and a recording time which is known in advance. If the remaining capacity of the storage medium is smaller than the required capacity of the storage medium, for example, a frame rate decimation and pixel reduction are performed upon a broadcast to be newly stored, a re-encoding processing is performed for the broadcast and then the resultant broadcast is stored in the storage medium. If the remaining storage capacity of the storage medium is larger than the required capacity of the storage medium and thus remains, a frame interpolation and pixel interpolation are performed for the broadcast to be stored and then a re-encoding processing is performed for the resultant broadcast in order to improve its image quality. As a result, recording of the broadcast data in the storage medium can be ensured.
摘要翻译： 当数字化的广播被记录在一个存储介质，所述存储介质的所需容量被首先数字化计算广播数据的比特率的基础上，并且预先已知的记录时间的所有上。 如果存储介质的剩余容量大于所述存储介质的所需容量小，例如，帧速率抽取和象素还原可应的广播进行新存储，再编码处理中进行用于广播和 然后将所得的广播被存储在存储介质中。 如果存储介质的剩余存储容量小于存储介质的所需容量较大，因此仍然存在，帧内插和像素内插执行用于广播被存储，然后再编码处理中进行对所产生的广播 为了提高图像质量。 其结果是，在存储介质中的广播数据的记录可以被保证。
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公开(公告)号：EP0665653B1
公开(公告)日：2001-12-05
申请号：EP95100985.1
申请日：1995-01-25
发明人： Takeno, Hiroshi , Miyagoshi, Eiji , Imanishi, Hiroshi , Nakatani, Shintarou , Akiyama, Toshihide
IPC分类号： H03M7/42
CPC分类号： H03M7/425
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公开(公告)号：EP0825781A3
公开(公告)日：2001-11-07
申请号：EP97113976.1
申请日：1997-08-13
发明人： Watabe, Akihiro , Miyagoshi, Eiji
IPC分类号： H04N7/50
CPC分类号： H04N19/427 , H04N19/423 , H04N19/61
摘要： A frame memory is provided which has five fields each having N slots, and three additional slots. Each slot has a storage capacity to store eight image lines. Four fields of the five fields serve to store motion compensation reference frames. The remaining one field and the three additional slots are used for B-picture interlace conversion. Disposed in a control unit are a slot control memory, a write slot pointer, and a read slot pointer. For an image output unit to acquire information from the frame memory in a correct slot order, the contents of the slot control memory are updated at the time of performing write operation to enter information into the frame memory by a bit stream analysis unit.
摘要翻译： 提供了具有五个字段的帧存储器，每个字段具有N个时隙和三个附加时隙。 每个插槽都有一个存储容量来存储八条图像线。 五个域中的四个域用于存储运动补偿参考帧。 剩余的一个场和三个附加时隙用于B图像交错变换。 在控制单元中设置有槽控制存储器，写入槽指针和读取槽指针。 为了图像输出单元以正确的时隙顺序从帧存储器获取信息，在执行写入操作时，时隙控制存储器的内容被更新，以由比特流分析单元将信息输入到帧存储器中。
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10.发明公开Apparatus and method for decoding variable-length code 失效Vorrichtung und Verfahren zur Dekodierung von Koden variablerLänge。
公开(公告)号：EP0665653A2
公开(公告)日：1995-08-02
申请号：EP95100985.1
申请日：1995-01-25
发明人： Takeno, Hiroshi , Miyagoshi, Eiji , Imanishi, Hiroshi , Nakatani, Shintarou , Akiyama, Toshihide
IPC分类号： H03M7/42
CPC分类号： H03M7/425
摘要： 5 n7 A variable-length-code decoder of this invention decodes an input bit stream including an input bit string having a codeword of a fixed-length code and a plurality of codewords of variable-length codes combined in a predetermined format. The decoder includes: a shifter for shifting the input bit string by a desired number of bits; a pattern detector for detecting a specific pattern in the bit string, and outputting a detection signal; two code tables provided for the respective variable-length codes, each code table having the length of each codeword (codeword length) and the decoded-word corresponding to the codeword, and outputting a codeword length and a decoded-word of a corresponding codeword based on the bit string output from the shifter; a processor for storing the format of the input bit string, outputting the length of the fixed-length code and decoded data of the fixed-length code, and selecting, for each of the variable-length codewords, one of the code tables to which the variable-length codeword belongs to, based on the detection signal and the format; a codelength selector for selecting the codeword length or the fixed-length code, and for setting the shift amount for the input bit string in the shifter; and an output circuit for selectively outputting the decoded-word or the decoded data.
摘要翻译： 本发明的可变长度码解码器对包括具有固定长度码的码字和以预定格式组合的可变长度码的多个码字的输入比特串进行解码输入比特流。 解码器包括：移位器，用于将输入位串移位所需位数; 用于检测比特串中的特定模式的模式检测器，并输出检测信号; 为每个可变长度码提供两个码表，每个码表具有每个码字的长度（码字长度）和与码字对应的解码字，并输出码字长度和相应码字的解码字 对来自移位器的位串输出; 用于存储输入比特串的格式的处理器，输出固定长度码的长度和固定长度码的解码数据，并且对于每个可变长度码字，选择一个码表，其中 可变长度码字基于检测信号和格式属于; 用于选择码字长度或固定长度码的码长选择器，以及用于设置移位器中输入比特串的移位量; 以及用于选择性地输出解码字或解码数据的输出电路。
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