公开(公告)号：EP3029839A1

公开(公告)日：2016-06-08

申请号：EP14831256.4

申请日：2014-06-09

申请人： Meisei Gakuen ,  Buffalo Memory Co., Ltd.

发明人： OTSUKA Kanji ,  SATO Yoichi ,  OKINAGA Takayuki ,  AZUMA Shuichiro

IPC分类号： H03K19/21 ,  G06F1/02

CPC分类号： H03K19/21 ,  G06F1/02

摘要： To provide an arithmetic logic device that achieves arithmetic processing in a relatively short time on a relatively small circuit scale.
[Solving Means]
There is provided the logic operation device including a memory device 12 configured to store a lookup table and receive the input of a bit string N bits long, N being an integer of at least 2, the input bit string representing the address in the lookup table at which is stored multiple-bit data of which a part includes a bit representative of the result of a logical operation performed between the bits included in the input bit string. The memory device 12 is accessed so as to output the bits included in the data stored at the address represented by the received bit string.

摘要翻译： 提供一种在相对较小的电路规模上在相当短的时间内实现算术处理的算术逻辑器件。 [解决方案]提供了包括存储器装置12的存储装置12，其被配置为存储查找表并接收N位长的位串的输入，N是至少为2的整数，输入的位串表示地址 在查找表中存储多位数据，其中的一部分包括表示在包括在输入位串中的位之间执行的逻辑运算的结果的位。 访问存储器件12以输出包含在存储在由接收的位串表示的地址处的数据中的位。

公开(公告)号：EP2282620A1

公开(公告)日：2011-02-09

申请号：EP09750642.2

申请日：2009-05-21

申请人： Meisei Gakuen ,  Shin-Etsu Polymer Co., Ltd.

发明人： OTSUKA Kanji ,  AKIYAMA Yutaka ,  KAWAGUCHI Toshiyuki ,  TAHARA Kazutoki

IPC分类号： H05K1/02 ,  H05K3/28 ,  H05K9/00

CPC分类号： H05K1/0234 ,  H05K1/0218 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/167 ,  H05K3/28 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09236

摘要： Disclosed is a paired low-characteristic impedance power line and ground line structure in which loop inductance is substantially 0. The paired low-characteristic impedance power line and ground line structure includes a laminated sheet (1) in which a metal wiring layer (20) having a power line (21) and a ground line (22) is provided on the surface of an insulating sheet (10), an insulating thin-film layer (31) provided so as to cover the power line (21) and the ground line (22), and a resistive layer (32) provided on the surface of the insulating thin-film layer (31).

摘要翻译： 公开了一种成对的低特性阻抗电源线和地线结构，其中回路电感基本上为0.成对的低特性阻抗电源线和地线结构包括层压板（1），其中金属布线层（20） 在绝缘片（10）的表面设置有电源线（21）和接地线（22）的绝缘薄膜层（31），覆盖电源线（21）和接地线 （22）以及设置在绝缘薄膜层（31）的表面上的电阻层（32）。

公开(公告)号：EP3029839B1

公开(公告)日：2018-05-30

申请号：EP14831256.4

申请日：2014-06-09

申请人： Meisei Gakuen ,  Buffalo Inc.

发明人： OTSUKA Kanji ,  SATO Yoichi ,  OKINAGA Takayuki ,  AZUMA Shuichiro

IPC分类号： H03K19/21 ,  G06F1/02

CPC分类号： H03K19/21 ,  G06F1/02

摘要： To provide an arithmetic logic device that achieves arithmetic processing in a relatively short time on a relatively small circuit scale. [Solving Means] There is provided the logic operation device including a memory device 12 configured to store a lookup table and receive the input of a bit string N bits long, N being an integer of at least 2, the input bit string representing the address in the lookup table at which is stored multiple-bit data of which a part includes a bit representative of the result of a logical operation performed between the bits included in the input bit string. The memory device 12 is accessed so as to output the bits included in the data stored at the address represented by the received bit string.