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公开(公告)号：EP2920881A2
公开(公告)日：2015-09-23
申请号：EP13796211.4
申请日：2013-11-15
发明人： DARMAWASKITA, Hartono , STEEDMAN, Sean, Stacy , GROZA, Cristian, Nicolae , MANCIOIU, Marilena , CHARAIS, John, Robert , LUNDSTRUM, Zeke
摘要： A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. The slope control unit comprises a capacitor coupled between an input and an output of the slope control unit, a switch for discharging the capacitor and a constant current source for charging the capacitor. Slope compensation parameters may be changed during operation with a programmable constant current source. The slope compensation module may also function as an analog sawtooth waveform frequency generator, and as an analog pulse width modulation (PWM) generator. Charging the capacitor generates a linearly decreasing (negative slope) ramp voltage for modulating a feedback error voltage into a slope compensated feedback error voltage. Capacitor charging may be controlled from a pulse width modulation signal. Opening of the switch may be programmably delayed, and a minimum closed time thereof may also be programmed during operation of the slope compensation module.
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公开(公告)号：EP2920882B1
公开(公告)日：2019-07-03
申请号：EP13798501.6
申请日：2013-11-15
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公开(公告)号：EP2920882A1
公开(公告)日：2015-09-23
申请号：EP13798501.6
申请日：2013-11-15
发明人： STEEDMAN, Sean, Stacy , LUNDSTRUM, Zeke , GROZA, Cristian, Nicolae , COPACIAN, Sebastian, Dan , DARMAWASKITA, Hartono
CPC分类号： G06F1/06 , G06F12/00 , G06F13/1694 , H03K5/05 , H03K5/1515 , H03K7/08 , H03L7/089 , H03L7/10 , Y02D10/14
摘要： A complementary output generator (COG) module generates at least two complementary outputs determined by rising and falling event sources. In a simple configuration of the COG module, the rising and falling event sources are the same signal which is a signal having the desired period and duty cycle. The COG module converts this single signal input into dual complementary outputs. The frequency and duty cycle of the dual outputs substantially match those of the single input signal. Blanking and deadband times may be introduced between the complementary outputs, and the dual complementary outputs may also be phase delayed. In addition the COG module may provide up to four outputs for controlling half and full-wave bridge power applications.
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5.发明授权DETECTING CONNECTION TO A USB HOST OR HUB WITHOUT USING AN EXTRA STATUS INPUT 有权连接到USB主机或集线器，而无需使用额外的状态输入检测
公开(公告)号：EP2115605B1
公开(公告)日：2010-08-18
申请号：EP08730948.0
申请日：2008-02-28
IPC分类号： G06F13/40
CPC分类号： G06F13/4081 , G06F1/3203 , G06F1/3253 , G06F2213/0042 , Y02D10/151 , Y02D50/20
摘要： A low power Universal Serial Bus (USB) capable device uses a weak pull-up resistance that is coupled to at least one data line of the USB for detection of when the USB capable device is connected to a USB host or hub. When the USB capable device is not connected to the USB host or hub, USB peripheral, including the USB transceiver, USB voltage regulator, serial interface and/or USB logic circuits required for USB operation may be powered down to conserve power drawn by the USB capable device. When the USB capable device is connected to the USB host or hub, a voltage from the weak pull-up will be significantly reduced, thus signaling that the USB peripheral and associated circuits should be powered up for normal USB operation.
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6.发明公开DETECTING CONNECTION TO A USB HOST OR HUB WITHOUT USING AN EXTRA STATUS INPUT 有权连接到USB主机或集线器，而无需使用额外的状态输入检测
公开(公告)号：EP2115605A1
公开(公告)日：2009-11-11
申请号：EP08730948.0
申请日：2008-02-28
IPC分类号： G06F13/40
CPC分类号： G06F13/4081 , G06F1/3203 , G06F1/3253 , G06F2213/0042 , Y02D10/151 , Y02D50/20
摘要： A low power Universal Serial Bus (USB) capable device uses a weak pull-up resistance that is coupled to at least one data line of the USB for detection of when the USB capable device is connected to a USB host or hub. When the USB capable device is not connected to the USB host or hub, USB peripheral, including the USB transceiver, USB voltage regulator, serial interface and/or USB logic circuits required for USB operation may be powered down to conserve power drawn by the USB capable device. When the USB capable device is connected to the USB host or hub, a voltage from the weak pull-up will be significantly reduced, thus signaling that the USB peripheral and associated circuits should be powered up for normal USB operation.
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公开(公告)号：EP1698053A1
公开(公告)日：2006-09-06
申请号：EP04814262.4
申请日：2004-12-15
IPC分类号： H03K17/22
CPC分类号： G06F1/24
摘要： A wake-up reset circuit is provided that generates a reset signal to a digital circuit upon a wake-up event. The wake-up reset circuit places the digital circuit into a known reset condition upon wake-up, even if a brown out condition occurs which may have caused unstable and unknown logic states in sequential circuit elements, e.g., volatile memory, flip flops and/or latching circuits. The wake-up reset circuit draws substantially no current when not generating the reset signal.
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公开(公告)号：EP1010249A1
公开(公告)日：2000-06-21
申请号：EP97949813.6
申请日：1997-11-29
CPC分类号： H03K5/153
摘要： A direct sensor interface (DSI) module which allows a microcontroller to directly interface to sensors having at least one of a resitive, capacitive, and/or current source characteristic. The DSI module (10) is coupled directly to a sensor device (12), which could be a reference resistor (12), which generates a sensor current (Is). A current mirroring circuit (24) outputs a charging current proportional to the sensor current (Is). A capacitive sensor (14) and/or a capacitive device is coupled to the current mirroring circuit (24) and generates a voltage when charged by the charging current. Using a comparator (16) and a threshold voltage source (nVREF), the time it takes the capacitive sensor (14) and/or a capacitive device to ramp up from zero to the threshold voltage can be measured. The charging time is proportional to the sensor reading.
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