公开(公告)号：EP1782427B1

公开(公告)日：2012-09-19

申请号：EP05786226.0

申请日：2005-08-16

申请人： Micron Technology, Inc.

发明人： BHATTACHARYYA, Arup ,  FORBES, Leonard

IPC分类号： G11C11/00

CPC分类号： G11C14/00 ,  G11C11/5621 ,  G11C11/5671 ,  G11C14/0018

公开(公告)号：EP1782427A1

公开(公告)日：2007-05-09

申请号：EP05786226.0

申请日：2005-08-16

申请人： MICRON TECHNOLOGY, INC.

发明人： BHATTACHARYYA, Arup ,  FORBES, Leonard

IPC分类号： G11C11/00

CPC分类号： G11C14/00 ,  G11C11/5621 ,  G11C11/5671 ,  G11C14/0018

摘要： An integrated DRAM-NVRAM (170, 171), multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate (120) floating plate (115, 116) device. The floating plate device (115, 116) provides enhanced charge storage for the DRAM part (104, 130, 101, 105, 131) of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate (100) with trenches that form pillars. A vertical wordline/gate (131, 130) on one side of a pillar is used to control the DRAM part (104, 130, 101, 105, 131, 103) of the cell. A vertical trapping layer (115, 116) on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate (120) is formed alongside the trapping layer and is shared with an adjacent floating plate device (115, 116).

公开(公告)号：EP1886356A1

公开(公告)日：2008-02-13

申请号：EP06770539.2

申请日：2006-05-17

申请人： Micron Technology, Inc.

发明人： BHATTACHARYYA, Arup

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L29/51

CPC分类号： H01L29/513 ,  B82Y10/00 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792 ,  Y10S438/954

摘要： Non- volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells in NOR or NAND memory architectures that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Memory cells of the present invention also allow multiple bit storage. These characteristics allow memory device embodiments of the present invention to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

公开(公告)号：EP1743339A2

公开(公告)日：2007-01-17

申请号：EP05740193.7

申请日：2005-04-28

申请人： MICRON TECHNOLOGY, INC.

发明人： BHATTACHARYYA, Arup

IPC分类号： G11C11/00 ,  H01L29/768

CPC分类号： H01L27/1027 ,  G11C11/39 ,  G11C16/349 ,  H01L21/28273 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/87

摘要： Disclosed herein is an improved thyristor-based memory cell. In one embodiment, the cell (10) is formed in a floating substrate using Silicon-On-Insulator (SOI) technology. The cell preferably incorporates a lateral thyristor (20) formed entirely in the floating substrate, and which is gated by a second word line. The cathode of the thyristor also comprises a source of an access transistor (18), whose drain is connected to the bit line of the device, and which is gated by a first word line (14). A trapping layer is built into the floating substrate, and when writing to the cell, pulses are added to cause holes to be trapped on the trapping layer for a logic state ‘1’ and to cause electrons to be trapped on the trapping layer for a logic state ‘0’. Trapping of charges on the trapping layer adds extra margin to the stored data states, prevents their degradation, and renders the cell non-volatile.

公开(公告)号：EP1743339B1

公开(公告)日：2011-10-05

申请号：EP05740193.7

申请日：2005-04-28

申请人： Micron Technology, Inc.

发明人： BHATTACHARYYA, Arup

IPC分类号： G11C11/39 ,  H01L29/768

CPC分类号： H01L27/1027 ,  G11C11/39 ,  G11C16/349 ,  H01L21/28273 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/87

摘要： Disclosed herein is an improved thyristor-based memory cell. In one embodiment, the cell (10) is formed in a floating substrate using Silicon-On-Insulator (SOI) technology. The cell preferably incorporates a lateral thyristor (20) formed entirely in the floating substrate, and which is gated by a second word line. The cathode of the thyristor also comprises a source of an access transistor (18), whose drain is connected to the bit line of the device, and which is gated by a first word line (14). A trapping layer is built into the floating substrate, and when writing to the cell, pulses are added to cause holes to be trapped on the trapping layer for a logic state ‘1’ and to cause electrons to be trapped on the trapping layer for a logic state ‘0’. Trapping of charges on the trapping layer adds extra margin to the stored data states, prevents their degradation, and renders the cell non-volatile.

公开(公告)号：EP2198457A2

公开(公告)日：2010-06-23

申请号：EP08838789.9

申请日：2008-09-23

申请人： Micron Technology, INC.

发明人： MIN, Kyu, S. ,  BREWER, Rhett, T. ,  KRISHNAMOHAN, Tejas ,  GRAETTINGER, Thomas, M. ,  RAMASWANY, D., V., Nirmal ,  WEIMER, Ronald, A. ,  BHATTACHARYYA, Arup

IPC分类号： H01L27/115

CPC分类号： G11C16/0483 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  Y10S977/943

摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

公开(公告)号：EP1908108A2

公开(公告)日：2008-04-09

申请号：EP06774620.6

申请日：2006-07-12

申请人： Micron Technology, Inc.

发明人： BHATTACHARYYA, Arup

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L21/8246 ,  G11C16/04

CPC分类号： H01L29/792 ,  G11C16/0475 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/42336 ,  H01L29/513 ,  H01L29/7881

摘要： Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non- volatile memory cells with band engineered gate-stacks that are placed above or below the channel region in front-side or back-side charge trapping gate- stack configurations in NAND memory array architectures. The band-gap engineered gate-stacks with asymmetric or direct tunnel barriers of the floating node memory cells of embodiments of the present invention allow for low voltage tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The memory cell architecture also allows for improved high density memory devices or arrays with the utilization of reduced feature word lines and vertical select gates.