摘要:
Provided is a semiconductor element in which atomic interdiffusion between a semiconductor region and an electrode is suppressed and increase in the contact resistance is suppressed even in cases where the semiconductor element is exposed to high temperatures during the production processes or the like. A semiconductor element of the present invention is provided with: a semiconductor region that contains silicon; an electrode that contains aluminum; and a diffusion barrier layer that is interposed between the semiconductor region and the electrode and contains germanium. The germanium content in at least a part of the diffusion barrier layer is 4 at% or more.
摘要:
A solid-state imaging device according to one embodiment is a multi-port solid-state imaging device, and includes an imaging region and a plurality of units. The imaging region includes a plurality of pixel columns. The units generate signals based on charges from the imaging region. Each or the units has an output register, a plurality of multiplication registers, and an amplifier. The output register transfers a charge from one or more corresponding pixel columns out of the plurality of pixel columns. The multiplication registers are provided in parallel, and receive the charge from the output register to generate multiplied charges individually. The amplifier generates a signal based on the multiplied charges from the multiplication registers.
摘要:
An image-sensing device has pixel areas for outputting CCD signals of plural channels, and an adjusting portion for adjusting a level of each channel of the CCD signals outputted from the pixel area. A first channel CCD signal is provided from a pixel area 11a, a horizontal OB area 15a, a slide shift area 12a, and an HCCD 13a. A second channel CCD signal is provided from a pixel area 11b, a horizontal OB area 15b, a slide shift area 12b, and an HCCD 13b. Both of the first and second CCD signals are supplied to the adjusting portion with a reference signal added. The adjusting portion controls CCD signal of each channel by making the level of reference signal the same. The variation of the shift efficiency of electric charge in the border of pixel areas 11a and 11b for each channel, and in the slide shift areas 13a and 13b can be compensated.
摘要:
Signal charges generated by a plurality of photoelectric conversion elements are transferred to first and second horizontal charge transfer registers via corresponding vertical charge transfer registers. The first and second horizontal charge transfer registers transfer the signal charges to first and second output portions, respectively. The first and second output portions convert the signal charges into voltages. The first and second output portions respectively include first and second signal charge detectors, first and second transistors each having a source, a drain, and a gate, and first and second charge sweeping regions, each having a charge sweeping control gate and a charge sweeping drain. The first signal charge detector, the source, the drain, and the gate of the first transistor, and the charge sweeping control gate and the charge sweeping drain of the first charge sweeping region are almost congruent to the second signal charge detector, the source, the drain, and the gate of the second transistor, and the charge sweeping control gate and the charge sweeping drain of the second charge sweeping region, and the former components are overlaid almost completely on the latter components by a translational movement.
摘要:
A CCD device incorporates Charge Multiplication in its CCD registers together with charge domain Dynamic Range compression. This structure preserves the high dynamic range available in the charge domain of these devices, and avoids limiting it by an inadequate voltage swing of the charge detection nodes and amplifiers. The Dynamic Range compression is logarithmic from a predetermined built in threshold and noiseless. The technique has an additional advantage of maintaining the compact size of the registers, and the registers may also include antiblooming devices to prevent blooming.
摘要:
An apparatus and method of equalizing a first (a) and second (b) charge packet. The apparatus includes a charge splitter for splitting the first charge packet (a) into a third charge packet (aa) on the first side of the charge splitter and a fourth charge packet (ab) on the second side of the charge splitter. The second charge packet is split into fifth charge packet (ba) on the first side of the charge splitter and a sixth charge packet (bb) on the second side of the charge splitter. The apparatus includes a charge combiner for adding the third (aa) and sixth (bb) charge packets and the fourth (ab) and fifth (ba) charge packets.
摘要:
An insulating layer in a field effect transistor is formed of superfine ceramic particles dispersed in a polymeric matrix. The characteristics of the insulating layer can be changed by varying the mix of ceramic particles and matrix components. Appropriate selection of components can provide a high dielectric constant material which is not subject to pinholes, has a high voltage breakdown and is chemically resistant. The material can be applied at relatively low processing temperatures, using a wide range of coating techniques, and is highly suited for use with polymeric substrates.
摘要:
Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.