公开(公告)号：EP2991118A4

公开(公告)日：2017-01-25

申请号：EP14764150

申请日：2014-03-09

申请人： JAPAN SCIENCE & TECH AGENCY

发明人： MAJIMA YUTAKA ,  TERANISHI TOSHIHARU ,  MATSUMOTO KAZUHIKO ,  MAEHASHI KENZO ,  SUSAKI TOMOFUMI ,  OHNO YASUHIDE ,  MATSUZAKI KOSUKE ,  HACKENBERGER GUILLAUME HUBERT FREDERIC

IPC分类号： H01L29/76 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7613 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0665 ,  H01L29/127 ,  H01L29/41725 ,  H01L29/4232 ,  H01L29/66439

摘要： Provided is a logical operation element that performs logical operations on three or more inputs using a single unique device. The logical operation element 30 is provided with an electrode 5A and the other electrode 5B that are provided to have a nanogap, a metal nanoparticle 7 arranged between the electrode 5A and the other electrode 5B in insulated state, and a plurality of gate electrodes 5C, 5D, 11, 11A, 11B for adjusting a charge of the metal nanoparticle 7. Electric current that flows between the electrode 5A and the other electrode 5B is controlled in accordance with the voltage applied to three or more of the gate electrodes 5C, 5D, 11, 11A, 11B.

公开(公告)号：EP3109628A1

公开(公告)日：2016-12-28

申请号：EP15173192.4

申请日：2015-06-22

申请人： Nokia Technologies Oy

发明人： Haque, MD Samiul ,  Borini, Stefano

IPC分类号： G01N27/414 ,  H01L29/423 ,  H01L29/772 ,  H01L29/40 ,  H01L29/06 ,  H01L29/12 ,  B82Y10/00 ,  B82Y15/00

CPC分类号： G01N27/4146 ,  B82Y10/00 ,  B82Y15/00 ,  G01N27/4148 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/423 ,  H01L29/4232 ,  H01L29/778 ,  H01L31/028 ,  H01L31/10 ,  Y02E10/547

摘要： An apparatus comprising a channel member (401), first and second electrodes (403, 404) configured to enable a flow of electrical current from the first electrode through the channel member to the second electrode, and a supporting substrate (402) configured to support the channel member and the first and second electrodes, wherein the channel member is separated from the supporting substrate by a nanomembrane (411) configured to facilitate the flow of electrical current through the channel member by inhibiting interactions between the channel member and supporting substrate. Possibly, between the substrate and the nanomembrane a conductive shield layer (412) is present, which may be a nanomembrane. The apparatus may also include a gate electrode (406) and a gate dielectric (407), which may be a nanomembrane. The apparatus may be configured to sense analyte species (513) as shown in Figure 5.

摘要翻译： 一种装置，包括通道构件（401），第一和第二电极（403,404），其被配置为使得能够从第一电极通过通道构件到第二电极的电流流动;以及支撑衬底（402） 所述通道构件和所述第一和第二电极，其中所述通道构件通过纳米膜（411）与所述支撑衬底分离，所述纳米膜构造成通过抑制所述通道构件和支撑衬底之间的相互作用来促进电流流过所述通道构件。 可能地，在衬底和纳米膜之间存在导电屏蔽层（412），其可以是纳米膜。 该装置还可以包括可以是纳米膜的栅电极（406）和栅极电介质（407）。 该装置可以被配置为感测如图5所示的分析物种（513）。

公开(公告)号：EP2991118A1

公开(公告)日：2016-03-02

申请号：EP14764150.0

申请日：2014-03-09

申请人： Japan Science and Technology Agency

发明人： MAJIMA, Yutaka ,  TERANISHI, Toshiharu ,  MATSUMOTO, Kazuhiko ,  MAEHASHI, Kenzo ,  SUSAKI, Tomofumi ,  OHNO, Yasuhide ,  MATSUZAKI, Kosuke ,  HACKENBERGER, Guillaume Hubert Frederic

IPC分类号： H01L29/66 ,  H01L29/06

CPC分类号： H01L29/7613 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0665 ,  H01L29/127 ,  H01L29/41725 ,  H01L29/4232 ,  H01L29/66439

摘要： Provided is a logical operation element that performs logical operations on three or more inputs using a single unique device. The logical operation element 30 is provided with an electrode 5A and the other electrode 5B that are provided to have a nanogap, a metal nanoparticle 7 arranged between the electrode 5A and the other electrode 5B in insulated state, and a plurality of gate electrodes 5C, 5D, 11, 11A, 11B for adjusting a charge of the metal nanoparticle 7. Electric current that flows between the electrode 5A and the other electrode 5B is controlled in accordance with the voltage applied to three or more of the gate electrodes 5C, 5D, 11, 11A, 11B.

摘要翻译： 提供了使用单个唯一设备对三个或更多个输入执行逻辑运算的逻辑运算元件。 逻辑运算元件30设置有电极5A，另一方的电极5B被设置为具有纳米间隙，在绝缘状态下配置在电极5A和另一电极5B之间的金属纳米粒子7，以及多个栅极电极5C， 5D，11,11A，11B，用于调整金属纳米颗粒7的电荷。在电极5A和另一个电极5B之间流动的电流根据施加到三个或更多个栅电极5C，5D， 11,11A，11B。

公开(公告)号：EP1290735B1

公开(公告)日：2011-11-16

申请号：EP01938146.6

申请日：2001-05-01

申请人： NXP B.V.

发明人： HUETING, Raymond, J., E. ,  HIJZEN, Erwin, A.

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L29/7835 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7834 ,  H01L29/8128

摘要： A semiconductor body has source and drain regions (4 and 5; 4' and 5') spaced apart by a body region (6; 6') and a drain drift region (50; 50') and both meeting the same surface (3a) of the semiconductor body. An insulated gate structure (7; 70'; 700) is provided within a trench (80; 80'; 80'') extending in the semiconductor body. The gate structure has a gate conductive region (70b; 70'b; 70''b) separated from the trench by a dielectric layer (70a; 70'a) such that a conduction channel accommodation portion (60; 60') of the body region extends along at least side walls (80a; 80'a; 80''a) of the trench and between the source (4; 4') and drain drift (50; 50') regions. The trench extends from the body region into the drain drift region (50; 50') and the dielectric layer has, at least on side walls (80a; 80'a; 80''a) of the trench, a greater thickness in the portion of the trench extending into the drain drift region (50; 50') than in the remaining portion of the trench so that an extension (71; 71'; 71''; 710) of the gate conductive region extending within the trench through the drain drift region (50; 50') towards the drain region (5; 5') forms a field plate.

公开(公告)号：EP2270843A2

公开(公告)日：2011-01-05

申请号：EP10184815.8

申请日：2002-08-16

申请人： Power Integrations, Inc.

发明人： Disney, Donald, R.

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/40 ,  H01L21/334 ,  H01L29/86 ,  H01L29/417 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/407 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7828 ,  Y10S438/925

摘要： A method of fabricating a high-voltage transistor (80) on a substrate (81,100), the method comprising:
forming a plurality of parallel arranged drift regions (82) comprising a doped semiconductor layer of a first conductivity type interleaved with an insulating layer (88,102) surrounding a conducting layer, the conducting layers each comprising a field plate member (84,103);
forming source (87,105) and body regions (86,107), the body regions separating the source regions from the drift regions; and
forming insulated gates (90) adjacent the body regions, the insulated gates defining channels in the body regions between the source regions and the drift regions.

摘要翻译： 一种在基板（81,100）上制造高电压晶体管（80）的方法，所述方法包括：形成多个平行布置的漂移区（82），所述漂移区包括与绝缘层交错的第一导电类型的掺杂半导体层 88,102），所述导电层各自包括场板构件（84,103）; 形成源极（87,105）和主体区域（86,107），所述主体区域将所述源极区域与所述漂移区域分开; 以及在所述主体区域附近形成绝缘栅极（90），所述绝缘栅极限定所述源极区域和所述漂移区域之间的体区域中的通道。

公开(公告)号：EP2264747A2

公开(公告)日：2010-12-22

申请号：EP10184810.9

申请日：2002-08-16

申请人： Power Integrations, Inc.

发明人： Disney, Donald, R.

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/40 ,  H01L21/334 ,  H01L29/86 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/407 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7828 ,  Y10S438/925

摘要： A method for fabricating a high-voltage transistor with an extended drain region comprises forming an epitaxial layer (101) on a substrate (100), the epitaxial layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair of spaced-apart trenches that define first and second sidewall portions of the epitaxial layer, wherein the mesa has a lateral width that is less than 20% of a depth of the trenches. A dielectric layer (102) is formed that partially fills each of the trenches, covering the first and second sidewall portions. The remaining portions of the trenches are then filled with a conductive material to form first and second field plate members (103) that are insulated from the substrate and the epitaxial layer.

摘要翻译： 一种用于制造具有延伸漏极区的高电压晶体管的方法包括在衬底（100）上形成外延层（101），所述外延层和衬底是第一导电类型; 然后蚀刻外延层以形成限定外延层的第一和第二侧壁部分的一对隔开的沟槽，其中台面的横向宽度小于沟槽深度的20％。 形成介电层（102），其部分地填充每个沟槽，覆盖第一和第二侧壁部分。 然后用导电材料填充沟槽的剩余部分，以形成与衬底和外延层绝缘的第一和第二场板构件（103）。

公开(公告)号：EP1973179A1

公开(公告)日：2008-09-24

申请号：EP07104436.6

申请日：2007-03-19

申请人： Hitachi Ltd.

发明人： Blackburn, Arthur Malcolm

IPC分类号： H01L51/05

CPC分类号： H01L51/0048 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/775 ,  H01L51/0012 ,  H01L51/0508

摘要： A method of guiding wire growth comprises providing a barrier for impeding wires, such as nanowires, during growth, providing a passage into the barrier, the passage having an opening on one side of the barrier, providing a region of catalyst for nucleating growth of wires adjacent to the barrier and outside the opening and arranging the barrier and the catalyst region on a surface of a substrate such that the barrier is arranged to impede wires growing across the surface.

摘要翻译： 引导线生长的方法包括：在生长过程中提供用于阻止线（例如纳米线）的屏障，提供通向阻挡层的通道，通道在阻挡层的一侧具有开口，提供用于成核电线生长的催化剂区域 邻近所述阻挡层并且在所述开口外部，并且将所述阻挡层和所述催化剂区域布置在基板的表面上，使得所述阻挡层被布置成阻止跨过所述表面生长的金属线。

公开(公告)号：EP1610372A3

公开(公告)日：2008-03-12

申请号：EP05011949.4

申请日：2005-06-02

申请人： VISHAY-SILICONIX

发明人： Xu, Robert

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08

CPC分类号： H01L29/7811 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4232 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7813

摘要： Here discussed is a method of fabricating a self-aligned contact in a semiconductor device which includes etching a trench in a core area and partially extending into a termination area of a substrate. A first oxide is grown on the substrate proximate the trench. A polysilicon layer is deposited in the core area and the termination area. The polysilicon layer is selectively etched to form a gate region in the core area portion of the trench. The etching of the polysilicon layer also forms a first portion of a gate interconnect region in the termination area portion of the trench and a second portion in the termination area outside of the trench. According to this method the gate contact opening is formed together with the body/source contact.

公开(公告)号：EP1692725B1

公开(公告)日：2008-03-05

申请号：EP04799251.6

申请日：2004-11-26

申请人： NXP B.V.

发明人： HUETING, Raymond, J., E.

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/41 ,  H01L29/423

CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7827 ,  H01L29/7831

摘要： The invention relates to a trench MOSFET with drain (8), sub-channel region (10) body (12) and source (14). The sub-channel region is doped to be the same conductivity type as the body (12), but of lower doping density. A field plate electrode (34) is provided adjacent to the sub-channel region (10) 10 and a gate electrode (32) next to the body (12).

公开(公告)号：EP1114466B1

公开(公告)日：2006-07-26

申请号：EP99929017.4

申请日：1999-04-22

申请人： Infineon Technologies AG

发明人： DEBOY, Gerald ,  STENGL, Jens-Peer ,  STRACK, Helmut ,  WEBER, Hans ,  GRAF, Heimo ,  RÜB, Michael ,  AHLERS, Dirk

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7825

摘要： The invention relates to a high-voltage semiconductor component comprising semiconductor areas (4, 5) of alternating, different conductivity types which are arranged in a semiconductor body in an alternating manner. In the semiconductor body said semiconductor areas extend from at least one first zone (6) to near a second zone (1) and are variably doped so that the electric field increases progressively from one zone to the other (6, 1).