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公开(公告)号：EP3301816A1
公开(公告)日：2018-04-04
申请号：EP15903530.2
申请日：2015-09-07
IPC分类号： H03M13/27
CPC分类号： H04L1/0071 , H03M13/2703 , H03M13/2792 , H03M13/2796 , H03M13/6508 , H03M13/6561 , H03M13/6563 , H04J3/1652 , H04J2203/0089 , H04L1/0041
摘要： An error correction encoder (10) includes an interleaver circuit (31), encoding circuits (32 1 , 32 2 ) and a deinterleaver circuit (33). The interleaver circuit (31) generates, in a standard speed mode, a single series of yet-to-be-coded bit sequences (IL 1 ) on the basis of the bits in plural columns that are arranged at an interval of C columns in a single series of transmission frames, and generates, in a two-times speed mode, two series of yet-to-be-coded bit sequences (IL 1 , IL 2 ) on the basis of the bits in plural columns that are arranged at an interval of C/2 columns in each of two series of transmission frames. The encoding circuits (32 1 , 32 2 ) apply error-correction coding to either the single series of yet-to-be-coded bit sequences (IL 1 ) or the two series of yet-to-be-coded bit sequences (IL 1 , IL 2 ).
摘要翻译： 纠错编码器（10）包括交织器电路（31），编码电路（321,322）和解交织器电路（33）。 交织器电路（31）在标准速度模式下，基于在C列中以C列间隔排列的多列中的比特来生成单个系列的待编码比特序列（IL1） 并且在2倍速模式下，基于以一定间隔排列的多列的比特，生成2个系列的未编码比特序列（IL1，IL2） C / 2列在两个系列传输帧中的每一个中。 编码电路（321,322）将纠错编码应用于单个未编码比特序列（IL1）或两个未编码比特序列（IL1，IL2）序列， 。
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公开(公告)号：EP2835909A1
公开(公告)日：2015-02-11
申请号：EP13769395.8
申请日：2013-01-15
IPC分类号： H03M13/19
CPC分类号： H03M13/1105 , H03M13/1102 , H03M13/1111 , H03M13/1191 , H03M13/336 , H03M13/3723 , H03M13/6325 , H04L1/0047 , H04L1/0057
摘要： A Sum-product decoder 17 carries out soft-decision iterative decoding on a received signal s'(t) received by a signal receiving unit 12 by using an extended check matrix H d which is a combination of a matrix D in which differential modulation by a differential modulator 3 is replaced by a check matrix and a check matrix H for error correcting codes to carry out error correction decoding on an information sequence b i .
摘要翻译： 和乘积解码器17通过使用扩展校验矩阵Hd对由信号接收单元12接收的接收信号s'（t）执行软判决迭代译码，该扩展校验矩阵Hd是矩阵D的组合， 差分调制器3被用于纠错码的校验矩阵和校验矩阵H代替以对信息序列bi执行纠错解码。
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公开(公告)号：EP3301816B1
公开(公告)日：2020-10-21
申请号：EP15903530.2
申请日：2015-09-07
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4.发明公开INPUT BIT-ERROR-RATE ESTIMATION METHOD AND INPUT BIT-ERROR-RATE ESTIMATION DEVICE 审中-公开输入位错误率估计方法和输入位错误率估计器
公开(公告)号：EP2680474A1
公开(公告)日：2014-01-01
申请号：EP12750102.1
申请日：2012-02-20
发明人： MIYATA, Yoshikuni , SUGIHARA, Kenya , ONOHARA, Kiyoshi , KUBO, Kazuo , YOSHIDA, Hideo , MIZUOCHI, Takashi
CPC分类号： G06F11/076 , H04L1/203
摘要： An input bit error ratio estimating method executed by a communication control unit includes a computing step (ST1), a condition determining step (ST2), a first input BER estimating step (ST3), a second input BER estimating step (ST4), a third input BER estimating step (ST5), and an input BER estimation result outputting step (ST6). In the condition determining step (ST2), the communication control unit determines which of a plurality of conditions (A to C) set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio (D r ). Based on the condition that is determined in the condition determining step (ST2) as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, processing of the step (ST3) to processing of the step (ST5), and executes the selected processing.
摘要翻译： 由通信控制单元执行的输入误码率估计方法包括计算步骤（ST1），条件确定步骤（ST2），第一输入BER估计步骤（ST3），第二输入BER估计步骤（ST4）， 第三输入BER估计步骤（ST5）和输入BER估计结果输出步骤（ST6）。 在条件判定步骤（ST2）中，通信控制单元基于内部解码残差检测比率（（ST2））来确定已经预先设置为缩小为1的多个条件（A至C）中的哪一个 博士）。 基于在条件确定步骤（ST2）中确定为已经建立的条件，通信控制单元从用于估计输入BER的多个处理过程中选择一个处理过程，即步骤（ST3）的处理， 到步骤（ST5）的处理，并执行所选择的处理。
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5.发明公开TEST MATRIX GENERATING METHOD, ENCODING METHOD, DECODING METHOD, COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, ENCODER AND DECODER 审中-公开测试矩阵生成方法，编码方法，解码方法，通信设备，通信系统，以及CODER解码器
公开(公告)号：EP1924001A1
公开(公告)日：2008-05-21
申请号：EP06782017.5
申请日：2006-07-31
CPC分类号： H03M13/116 , H03M13/1117 , H03M13/1122 , H03M13/1137 , H03M13/6362 , H04L1/0057
摘要： A processing of preparing a regular quasi-cyclic matrix in which cyclic permutation matrices are arranged in row and column directions and specific regularity is given to the cyclic permutation matrices, deriving conditional expressions for assuring a predetermined minimum loop in the parity check matrix to be finally generated, and generating a mask matrix for converting a specific cyclic permutation matrix into a zero-matrix based on the conditional expressions and a predetermined weight distribution, a processing of converting the specific cyclic permutation matrix in the regular quasi-cyclic matrix into the zero-matrix using the mask matrix to generate an irregular masking quasi-cyclic matrix, and a processing of generating an irregular parity check matrix with an LDGM structure in which the masking quasi-cyclic matrix, and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location are performed.
摘要翻译： 制备其中循环置换矩阵中的行和列的方向和特定规律性布置在正则的准循环矩阵的处理被提供给循环置换矩阵，导出条件表达式用于确保预定的最小循环中的奇偶校验矩阵是最后 产生的，并且对于一个特定的循环置换矩阵变换成基于所述条件表达式和预定的重量分布，特定的循环置换矩阵变换在正则的准循环矩阵到零的处理的零矩阵生成掩码矩阵 矩阵使用掩模矩阵，以产生不规则准循环矩阵的掩蔽，并在LDGM结构，在无规律的奇偶校验矩阵生成的处理，其中，掩蔽准循环矩阵，并且其中所述循环置换矩阵中布置在矩阵 阶梯方式在预定位置排列被执行。
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6.发明公开
公开(公告)号：EP2892158A1
公开(公告)日：2015-07-08
申请号：EP13832457.9
申请日：2013-08-27
发明人： MATSUMOTO, Wataru , AKINO, Toshiaki , MIYATA, Yoshikuni , SUGIHARA, Kenya , SUGIHARA, Takashi , FUJIMORI, Takafumi
CPC分类号： H04L7/0016 , H03M13/1105 , H03M13/1515 , H03M13/152 , H03M13/45 , H03M13/63 , H04B1/76 , H04L1/005 , H04L1/0057 , H04L7/0079 , H04L7/033
摘要： A receiver, a transmitter, and a communication method, which exhibit performance close to that of synchronous detection even when a phase slip occurs, are obtained. Provided are a transmitter (10) for transmitting a transmission signal subjected to modulation after error correction coding and a receiver (20) including a phase compensation unit (21, 22) for receiving the transmission signal and performing demodulation therefor while maintaining synchronization thereof and an error correction decoding unit (23 to 25) for performing decoding processing for received data that has been subjected to the demodulation. The transmitter transmits a signal formed of a plurality of pilot sequences as a part of the transmission signal, and the receiver has a phase slip estimation processing function for estimating the phase slip by the phase compensation unit by using the plurality of pilot sequences, and for estimating a phase difference component by the error correction decoding unit, to thereby correct a phase of the received data.
摘要翻译： 获得即使发生相移也表现出接近于同步检测性能的接收机，发射机和通信方法。 提供了一种用于发送经纠错编码后进行调制的发送信号的发送机（10）和包括相位补偿单元（21,22）的接收机（20,22），用于接收发送信号并对其进行解调同时保持同步， 用于对经过解调的接收数据执行解码处理的纠错解码单元（23至25）。 发射机发送由多个导频序列形成的信号作为发送信号的一部分，并且接收机具有相位偏移估计处理功能，用于通过使用多个导频序列来估计相位补偿单元的相位滑移，并且对于 通过纠错解码单元估计相位差分量，从而校正接收数据的相位。
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7.发明公开ERROR CORRECTION CODING DEVICE, ERROR CORRECTION DECODING DEVICE AND METHOD THEREFOR 审中-公开FEHLERKORREKTUR-KODIERUNGSVORRICHTUNG，FEHLERKORREKTUR-DEKODIERUNGSVORRICHTUNG UND VERFAHRENDAFÜR
公开(公告)号：EP2717479A1
公开(公告)日：2014-04-09
申请号：EP12792209.4
申请日：2012-05-30
IPC分类号： H03M13/29
CPC分类号： H03M13/29 , H03M13/1102 , H03M13/1145 , H03M13/152 , H03M13/2909 , H03M13/356
摘要： Provided is an error correction encoder that performs coding on both a transmission area and a redundancy area of the transmission frame by using a product code, and when excess or deficiency is arisen with respect to allocation of an information sequence area and/or a parity sequence area in a product code frame generated by the coding using the product code, non-uniformly allocate the information sequence area to the parity sequence area, and/or non-uniformly allocate the parity sequence area to the information sequence area, where each of the non-uniform allocations is performed in accordance with the arisen excess or deficiency.
摘要翻译： 提供了一种纠错编码器，其通过使用乘积代码对发送帧的发送区域和冗余区域两者进行编码，并且当相对于信息序列区域和/或奇偶校验序列的分配产生过多或不足时 通过使用产品代码的编码生成的商品代码帧中的区域，将信息序列区域均匀地分配给奇偶校验序列区域，和/或非均匀地将奇偶校验序列区域分配给信息序列区域，其中， 根据发生的过量或不足，进行非均匀分配。
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8.发明公开ERROR CORRECTION METHOD AND DEVICE, AND COMMUNICATION SYSTEM USING THE SAME 有权FEHLERKORREKTURVERFAHREN UND -ORRICHTUNG SOWIE KOMMUNIKATIONSSYSTEM DAMIT
公开(公告)号：EP2503698A1
公开(公告)日：2012-09-26
申请号：EP10831506.0
申请日：2010-11-11
IPC分类号： H03M13/19
CPC分类号： H03M13/1102 , H03M13/1174 , H03M13/1182 , H03M13/35 , H03M13/6516
摘要： An error correction method and device as well as a communication system using them are obtained in which an LDPC code generation method capable of adjusting an code rate of an LDPC code in a variable manner while leaving the length of the code constant, is achieved by the use of an efficient encoding method or means supporting a variable code rate, so that the code rate of the LDPC code can be adjusted without changing the code length.
An error correction method according to this invention is provided with a row splitting step (S3) to split each of a part or all of rows into two or more rows based on one parity check matrix, and a code construction step to construct a plurality of LDPC codes with arbitrary code rates, respectively.摘要翻译： 获得纠错方法和装置以及使用它们的通信系统，其中可以通过以下方式实现能够以可变方式调整LDPC码的码率同时保持码长度的LDPC码生成方法： 使用支持可变码率的有效编码方法或装置，使得可以在不改变码长的情况下调整LDPC码的码率。 根据本发明的纠错方法具有行划分步骤（S3），用于基于一个奇偶校验矩阵将行的一部分或全部行分成两行或更多行，以及代码构建步骤，用于构建多个 分别具有任意码率的LDPC码。
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公开(公告)号：EP4428463A1
公开(公告)日：2024-09-11
申请号：EP21967997.4
申请日：2021-12-13
发明人： MARIYAMA, Toshisada , HOKARI, Hiroaki , YOSHIKAWA, Nobuyuki , YOSHIMURA, Genta , MIYATA, Yoshikuni , YOKOSUKA, Yusuke
IPC分类号： F24F11/64
CPC分类号： F24F11/64 , G05B13/048 , G05B13/0265 , G05B13/02
摘要： An apparatus control device (3) is configured to include an observed value acquiring unit (11) that acquires, from a sensor (2-n) (n=1, ..., N) that observes an environment in which a control target apparatus is installed, an observed value of the environment, an observation predicted value acquiring unit (12) that gives an observed value acquired by the observed value acquiring unit (11) to a first learning model (12a) and acquires an observation predicted value that is a future observed value from the sensor (2-n) from the first learning model (12a), and an unobservable value acquiring unit (13) that gives an observed value acquired by the observed value acquiring unit (11) to a second learning model (13a) and acquires an unobservable value that is a value not directly observed by the sensor (2-n) from the second learning model (13a). In addition, the apparatus control device (3) includes a control value calculating unit (14) that calculates a control value of the control target apparatus using the observed value acquired by the observed value acquiring unit (11), the observation predicted value acquired by the observation predicted value acquiring unit (12), and the unobservable value acquired by the unobservable value acquiring unit (13).
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公开(公告)号：EP3119051B1
公开(公告)日：2019-11-20
申请号：EP15760950.4
申请日：2015-02-16
IPC分类号： H04L27/38 , H04L25/06 , H04L27/233 , H04L27/34
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