公开(公告)号：EP2717479B1

公开(公告)日：2018-12-26

申请号：EP12792209.4

申请日：2012-05-30

申请人： Mitsubishi Electric Corporation

发明人： MIYATA, Yoshikuni ,  MATSUMOTO, Wataru ,  YOSHIDA, Hideo ,  KUBO, Kazuo

IPC分类号： H03M13/29 ,  H03M13/35 ,  H03M13/11 ,  H03M13/45 ,  H03M13/15

CPC分类号： H03M13/29 ,  H03M13/1102 ,  H03M13/1145 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/356

摘要： Provided is an error correction encoder that performs coding on both a transmission area and a redundancy area of the transmission frame by using a product code, and when excess or deficiency is arisen with respect to allocation of an information sequence area and/or a parity sequence area in a product code frame generated by the coding using the product code, non-uniformly allocate the information sequence area to the parity sequence area, and/or non-uniformly allocate the parity sequence area to the information sequence area, where each of the non-uniform allocations is performed in accordance with the arisen excess or deficiency.

公开(公告)号：EP2819310A1

公开(公告)日：2014-12-31

申请号：EP13305884.2

申请日：2013-06-26

申请人： ALCATEL LUCENT

发明人： Razzetti, Luca Gabriele ,  Costantini, Carlo ,  Pepe, Marianna ,  Gavioli, Giancarlo

IPC分类号： H03M13/11

CPC分类号： H03M13/1145 ,  H03M13/1128

摘要： It is disclosed a forward error correction decoder for a network element of a communication network. The decoder comprises a first decoding stage configured to receive an input data block, the first decoding stage comprising a plurality of decoding units connected in cascade, each of said decoding units being configured to perform one iteration of a forward error correction decoding procedure on said input data block. The first decoding stage is further configured to output an output data block. The decodes also comprises a second decoding stage comprising a further decoding unit configured to: receive the output data block in case the output data block is not correct; and perform a number of further iterations of the forward error correction decoding procedure on the output data block until a termination condition is fulfilled, the number of further iterations being equal to or higher than 1.

摘要翻译： 公开了一种用于通信网络的网元的前向纠错解码器。 解码器包括被配置为接收输入数据块的第一解码级，第一解码级包括级联连接的多个解码单元，每个解码单元被配置为对所述输入执行前向纠错解码过程的一次迭代 数据块。 第一解码级还被配置为输出输出数据块。 解码还包括第二解码级，其包括另外的解码单元，其被配置为：在输出数据块不正确的情况下接收输出数据块; 并且对输出数据块执行前向纠错解码过程的多个进一步迭代，直到满足终止条件，进一步迭代次数等于或高于1。

公开(公告)号：EP2270990A3

公开(公告)日：2011-06-22

申请号：EP10178046.8

申请日：2004-04-19

申请人： Sony Corporation

发明人： Yokokawa, Takashi ,  Miyauchi, Toshiyuki ,  Iida, Yasuhiro

IPC分类号： H03M13/11

CPC分类号： H03M13/1168 ,  H03M13/11 ,  H03M13/1114 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1145 ,  H03M13/1188 ,  H03M13/6505 ,  H03M13/6566 ,  H03M13/6577

摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P × P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P × P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculation.

公开(公告)号：EP2625787A2

公开(公告)日：2013-08-14

申请号：EP11773571.2

申请日：2011-10-04

申请人： NEC Corporation ,  Technische Universität Dresden

发明人： KOBORI, Tomoyoshi ,  KUNZE, Steffen ,  MATUS, Emil ,  FETTWEIS, Gerhard

IPC分类号： H03M13/11 ,  H03M13/29

CPC分类号： G06F11/1044 ,  G06F5/015 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/114 ,  H03M13/1145 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/2775 ,  H03M13/296 ,  H03M13/2978 ,  H03M13/6508 ,  H03M13/6513 ,  H03M13/6566 ,  H03M13/6569 ,  H03M13/6577

摘要： In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.

公开(公告)号：EP2270989A2

公开(公告)日：2011-01-05

申请号：EP10178005.4

申请日：2004-04-19

申请人： Sony Corporation

发明人： Yokokawa, Takashi ,  Miyauchi, Toshiyuki ,  Iida, Yasuhiro

IPC分类号： H03M13/11

CPC分类号： H03M13/1168 ,  H03M13/11 ,  H03M13/1114 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1145 ,  H03M13/1188 ,  H03M13/6505 ,  H03M13/6566 ,  H03M13/6577

摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P × P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P × P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.

摘要翻译： 本发明涉及一种用于实现LDPC码的解码的解码装置和解码方法，其中在抑制电路规模的同时，可以在足够可行的范围内抑制工作频率，并且可以执行存储器存取的控制 很容易，也是一个程序。 LDPC码的校验矩阵由（P×P）个单位矩阵，单位矩阵中的1至数个1被0替代的矩阵，循环移位的矩阵，矩阵， 它们是两个或更多个的和，（P×P）0矩阵的和。 校验节点计算器313同时执行p校验节点计算。 可变节点计算器319同时执行p个可变节点计算。

公开(公告)号：EP1442527A1

公开(公告)日：2004-08-04

申请号：EP02800936.3

申请日：2002-10-07

申请人： Flarion Technologies, INC.

发明人： RICHARDSON, Tom ,  NOVICHKOV, Vladimir

IPC分类号： H03M13/00 ,  G06E1/00

CPC分类号： H03M13/1137 ,  G06N3/02 ,  H03M13/1102 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1125 ,  H03M13/1131 ,  H03M13/1134 ,  H03M13/1145 ,  H03M13/6362 ,  H03M13/6502 ,  H03M13/6577 ,  H03M13/658 ,  H03M13/6583

摘要： Techniques for implementing message passing decoders, e.g., LDPC decoders, are described. To facilitate hardware implementation messages are quantized to integer multiples of ½ ln2. Messages are transformed between more compact variable and less compact constraint node message representation formats. The variable node message format allows variable node message operations to be performed through simple additions and subtractions while the constraint node representation allows constraint node message processing to be performed through simple additions and subtractions. Variable and constraint nodes are implemented using an accumulator module (1302), subtractor module (1304) and delay pipeline (1306). The accumulator module (1302) generates an accumulated message sum (1316). The accumulated message sum (1316) for a node is stored and then delayed input messages from the delay pipeline (1306) are subtracted there from to generate output messages (1321). The delay pipeline (1306) includes a variable delay element making it possible to sequentially perform processing operations corresponding to nodes of different degrees.

公开(公告)号：EP1158682A3

公开(公告)日：2003-09-10

申请号：EP01304531.5

申请日：2001-05-23

申请人： Agere Systems Guardian Corporation

发明人： Blanksby, Andrew J. ,  Howland, Christopher John

IPC分类号： H03M13/39

CPC分类号： H03M13/1145 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1134 ,  H03M13/1174 ,  H03M13/1191 ,  H03M13/15 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/2957

摘要： A block-parallel decoding algorithm and corresponding decoder architecture utilizes a set of interconnected processing nodes configured in the form of a probability dependency graph. The probability dependency graph is characterized at least in part by a code used to encode blocks of bits or symbols, and the processing nodes implement a block-parallel decoding process for blocks of the bits or symbols to be decoded. The probability dependency graph may be, for example, a bipartite probability dependency graph which includes a set of N variable nodes and a set of T check nodes, with one of the N variable nodes being associated with each of N bits or symbols of a given block to be decoded. A single iteration of the block-parallel decoding process produces within the variable nodes an updated estimate for every bit or symbol in the given block, and may produce within the variable nodes an a-posteriori probability associated with the decoded bit or symbol for a soft-decision decoder. As another example, the probability dependency graph may be in the form of a directional probability dependency graph with multiple levels of nodes including an initial level, at least one intermediate level and a final level, arranged such that calculations can be performed at each level without sequential intra-block dependencies. The outputs of the nodes of the final level give an estimate of the transmitted bits or symbols for the given block, and may provide an estimate of the corresponding a-posteriori probabilities for a soft-decision decoder.

公开(公告)号：EP1158682A2

公开(公告)日：2001-11-28

申请号：EP01304531.5

申请日：2001-05-23

申请人： Agere Systems Optoelectronics Guardian Corporation

发明人： Blanksby, Andrew J. ,  Howland, Christopher John

IPC分类号： H03M13/39 ,  H03M13/47

CPC分类号： H03M13/1145 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1134 ,  H03M13/1174 ,  H03M13/1191 ,  H03M13/15 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/2957

摘要： A block-parallel decoding algorithm and corresponding decoder architecture utilizes a set of interconnected processing nodes configured in the form of a probability dependency graph. The probability dependency graph is characterized at least in part by a code used to encode blocks of bits or symbols, and the processing nodes implement a block-parallel decoding process for blocks of the bits or symbols to be decoded. The probability dependency graph may be, for example, a bipartite probability dependency graph which includes a set of N variable nodes and a set of T check nodes, with one of the N variable nodes being associated with each of N bits or symbols of a given block to be decoded. A single iteration of the block-parallel decoding process produces within the variable nodes an updated estimate for every bit or symbol in the given block, and may produce within the variable nodes an a-posteriori probability associated with the decoded bit or symbol for a soft-decision decoder. As another example, the probability dependency graph may be in the form of a directional probability dependency graph with multiple levels of nodes including an initial level, at least one intermediate level and a final level, arranged such that calculations can be performed at each level without sequential intra-block dependencies. The outputs of the nodes of the final level give an estimate of the transmitted bits or symbols for the given block, and may provide an estimate of the corresponding a-posteriori probabilities for a soft-decision decoder.

摘要翻译： 块并行解码算法和相应的解码器架构利用以概率依赖图的形式配置的一组互连处理节点。 概率依赖图至少部分地由用于编码位或符号块的代码表征，并且处理节点对要解码的比特或符号的块实施块并行解码处理。 概率依赖图可以是例如包括一组N个可变节点和一组T个校验节点的二分概率依赖图，其中N个可变节点中的一个与给定的N个比特或符号中的每一个相关联 要解码的块。 块并行解码过程的单个迭代在可变节点内产生给定块中的每个位或符号的更新估计，并且可以在可变节点内产生与解码的位或符号相关联的软件的后验概率 决定解码器。 作为另一示例，概率依赖图可以是具有包括初始级别，至少一个中间级别和最终级别的多个级别的节点的方向概率依赖图的形式，使得可以在每个级别执行计算，而不进行计算 顺序块内依赖。 最终级别的节点的输出给出给定块的发送比特或符号的估计，并且可以提供对于软判决解码器的对应的后验概率的估计。

公开(公告)号：EP2892157A1

公开(公告)日：2015-07-08

申请号：EP14305002.9

申请日：2014-01-02

申请人： ALCATEL LUCENT

发明人： Schmalen, Laurent

IPC分类号： H03M13/11 ,  H03M13/37 ,  H03M13/15 ,  H03M13/29

CPC分类号： H03M13/112 ,  H03M13/1117 ,  H03M13/1145 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/3707 ,  H03M13/6577 ,  H03M13/6583

摘要： Embodiments relate to a decoder (500) for iteratively decoding an LDPC encoded code word. The decoder comprises a decoding module (502) to decode the LDPC encoded code word according to an offset min-sum decoding rule applying at least one offset correction value ( β 1 ; β 2 ) to a min-sum check-node update operation. The decoder (500) further includes a processor (506) to select, from a plurality of computation rules, a computation rule for the at least one offset correction value ( β 1 ; β 2 ) dependent on a selection criterion.

摘要翻译： 实施例涉及用于迭代地解码LDPC编码码字的解码器（500）。 解码器包括解码模块（502），用于根据将至少一个偏移校正值（2; 2）应用于最小和校验节点更新操作的偏移最小和解码规则对LDPC编码码字进行解码。 解码器（500）还包括处理器（506），用于根据选择标准从多个计算规则中选择用于所述至少一个偏移校正值（²1;²2）的计算规则。

公开(公告)号：EP2717479A4

公开(公告)日：2015-05-27

申请号：EP12792209

申请日：2012-05-30

申请人： MITSUBISHI ELECTRIC CORP

发明人： MIYATA YOSHIKUNI ,  MATSUMOTO WATARU ,  YOSHIDA HIDEO ,  KUBO KAZUO

IPC分类号： H03M13/29 ,  H03M13/11 ,  H03M13/35 ,  H03M13/45

CPC分类号： H03M13/29 ,  H03M13/1102 ,  H03M13/1145 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/356

摘要： Provided is an error correction encoder that performs coding on both a transmission area and a redundancy area of the transmission frame by using a product code, and when excess or deficiency is arisen with respect to allocation of an information sequence area and/or a parity sequence area in a product code frame generated by the coding using the product code, non-uniformly allocate the information sequence area to the parity sequence area, and/or non-uniformly allocate the parity sequence area to the information sequence area, where each of the non-uniform allocations is performed in accordance with the arisen excess or deficiency.